component
CDC421A156RGER
Public Made by Adomby adom
Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDC421A156RGER
Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-24-EP(4x4)
CDC421A156RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE | input | Chip enable LVCMOS input: CE = 1 enables the device and outputs, while CE = 0 disables all current sources so LVPECL outputs go Hi-Z. |
| 2 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 3 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 4 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 5 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 6 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 7 | OUTN | output | High-speed negative differential LVPECL output, enabled by the CE pin. |
| 8 | GND | power_in | Ground pin for the device network ground. |
| 9 | GND | power_in | Ground pin for the device network ground. |
| 10 | OUTP | output | High-speed positive differential LVPECL output, enabled by the CE pin. |
| 11 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 12 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 13 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 14 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 15 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 16 | VCC | power_in | 3.3-V power supply; recommended supply range is 3.0 V to 3.60 V. |
| 17 | VCC | power_in | 3.3-V power supply; recommended supply range is 3.0 V to 3.60 V. |
| 18 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 19 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 20 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 21 | XIN1 | input | In crystal input mode connects to one end of the crystal; in LVCMOS single-ended driven mode it is the input reference. |
| 22 | XIN2 | input | Connects to the other end of the crystal in crystal mode; in LVCMOS single-ended driven mode it should be connected to GND. |
| 23 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 24 | NC | unconnected | TI test pin; do not connect, leave floating. |
| 25 | Thermal pad | passive | Exposed thermal pad on the package bottom; it must be soldered to the printed circuit board for thermal and mechanical performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | RTC/Clock Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 4.6 | V | 2 | ||
| Voltage range for all other input pins | VI | -0.5 | V | Upper limit printed as VCC to +0.5 V | 2 | ||
| Output current for LVPECL | IO | -50 | mA | 2 | |||
| Electrostatic discharge (HBM) | ESD | 2 | kV | HBM | 2 | ||
| Specified free-air temperature range | TA | -40 | 85 | °C | No airflow | 2 | |
| Maximum junction temperature | TJ | 125 | °C | 2 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 2 | ||
| Supply voltage | VCC | 3 | 3.3 | 3.6 | V | 2 | |
| Ambient temperature | TA | -40 | 85 | °C | No airflow, no heatsink | 2 | |
| Supply voltage | VCC | 3 | 3.3 | 3.6 | V | Over recommended operating conditions | 3 |
| Total current | IVCC | 91 | 110 | mA | Over recommended operating conditions | 3 | |
| Output frequency | fCLK | 100 | 312.5 | MHz | LVPECL output; family range across all output frequencies | 3 | |
| LVPECL differential output voltage | /VOD/ | 407 | 1076 | mV | 3 | ||
| Duty cycle of the output waveform | 45 | 55 | % | Duty cycle of the output waveform | 3 | ||
| Low-level CMOS input current | IL, CMOS | -200 | µA | VCC = VCC, max, VIL = 0.0 V | 3 | ||
| High-level CMOS input current | IH, CMOS | 200 | µA | VCC = VCC, min, VIH = 3.7 V | 3 | ||
| Output rise time | tR | 230 | ps | 20% to 80% of VOUT(PP) | 3 | ||
| Output fall time | tF | 230 | ps | 20% to 80% of VOUT(PP) | 3 | ||
| RMS jitter | tj | 1 | ps, RMS | 10 kHz to 20 MHz | 3 | ||
| Phase noise at 100 Hz | phn100 | -106 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 1 kHz | phn1k | -117 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 10 kHz | phn10k | -126 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 100 kHz | phn100k | -128 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 1 MHz | phn1M | -139 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 10 MHz | phn10M | -147 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Phase noise at 20 MHz | phn20M | -147 | dBc/Hz | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| RMS jitter integrated from 12 kHz to 20 MHz | JRMS | 472 | fs | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Total jitter | Tj | 31.54 | ps | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 | ||
| Deterministic jitter | Dj | 9.12 | ps | LVCMOS input 31.2500 MHz; LVPECL output 156.25 MHz | 6 |
CAD (KiCad official)
- Symbol:
CDC421A156RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
cdc421a156rger-etched.step/cdc421a156rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdc421a156rger.step/cdc421a156rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
8bd3605254dfeec2, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).