component
CDC391D
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDC391D
Texas Instruments · Clock Buffers, Drivers · SOIC-16
CDC391D from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the device has distributed GND pins (1, 4, 7) to reduce switching noise. |
| 2 | 1Y2 | tri_state | Bank 1 clock output, true or complementary per 1T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
| 3 | 1Y3 | tri_state | Bank 1 clock output, true or complementary per 1T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
| 4 | GND | power_in | Ground pin; the device has distributed GND pins (1, 4, 7) to reduce switching noise. |
| 5 | 2Y1 | tri_state | Bank 2 clock output, true or complementary per 2T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
| 6 | 2Y2 | tri_state | Bank 2 clock output, true or complementary per 2T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
| 7 | GND | power_in | Ground pin; the device has distributed GND pins (1, 4, 7) to reduce switching noise. |
| 8 | 3Y1 | tri_state | Bank 3 clock output, true or complementary per 3T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
| 9 | OE | input | Output-enable input; when high, all Y outputs are placed in the high-impedance state per the function table. |
| 10 | 3T/C | input | Polarity-control input for bank 3; low gives true outputs (Y follows A) and high gives complementary outputs (Y inverts A). |
| 11 | VCC | power_in | Supply voltage pin; recommended VCC is 4.75 V to 5.25 V (5 V nominal), with distributed VCC pins to reduce switching noise. |
| 12 | A | input | Clock input that distributes to all six Y outputs; input clock frequency up to 100 MHz with input transition rate of 5 ns/V maximum. |
| 13 | 2T/C | input | Polarity-control input for bank 2; low gives true outputs (Y follows A) and high gives complementary outputs (Y inverts A). |
| 14 | VCC | power_in | Supply voltage pin; recommended VCC is 4.75 V to 5.25 V (5 V nominal), with distributed VCC pins to reduce switching noise. |
| 15 | 1T/C | input | Polarity-control input for bank 1; low gives true outputs (Y follows A) and high gives complementary outputs (Y inverts A). |
| 16 | 1Y1 | tri_state | Bank 1 clock output, true or complementary per 1T/C, with high-drive capability of −48 mA IOH and 48 mA IOL, and high-impedance when OE is high. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | RTC/Clock Chip |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CDC391D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cdc391d-etched.step/cdc391d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdc391d.step/cdc391d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (9 pp, sha256
4ed073ab6061c2c0, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).