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CD74HCT75M
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Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HCT75M++**Texas Instruments** · Latches · SOIC-16++CD74HCT75M from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1Q0̅ | output | Complementary output of latch 0 of the first 2-bit latch; drives 10 LSTTL loads (standard output). |+| 2 | 1D0 | input | Data input 0 of the first latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load). |+| 3 | 1D1 | input | Data input 1 of the first latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load). |+| 4 | 2E | input | Enable input for the second 2-bit latch; data enters the latch and appears at Q when E is HIGH, output is not affected when LOW (1.2 unit loads). |+| 5 | VCC | power_in | Supply voltage, 4.5V to 5.5V for HCT types (absolute maximum -0.5V to 7V). |+| 6 | 2D0 | input | Data input 0 of the second latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load). |+| 7 | 2D1 | input | Data input 1 of the second latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load). |+| 8 | 2Q1̅ | output | Complementary output of latch 1 of the second 2-bit latch; drives 10 LSTTL loads (standard output). |+| 9 | 2Q1 | output | True output of latch 1 of the second 2-bit latch; drives 10 LSTTL loads (standard output). |+| 10 | 2Q0 | output | True output of latch 0 of the second 2-bit latch; drives 10 LSTTL loads (standard output). |+| 11 | 2Q0̅ | output | Complementary output of latch 0 of the second 2-bit latch; drives 10 LSTTL loads (standard output). |+| 12 | GND | power_in | Ground (0V reference); DC VCC or ground current limit is ±50mA. |+| 13 | 1E | input | Enable input for the first 2-bit latch; data enters the latch and appears at Q when E is HIGH, output is not affected when LOW (1.2 unit loads). |+| 14 | 1Q1̅ | output | Complementary output of latch 1 of the first 2-bit latch; drives 10 LSTTL loads (standard output). |+| 15 | 1Q1 | output | True output of latch 1 of the first 2-bit latch; drives 10 LSTTL loads (standard output). |+| 16 | 1Q0 | output | True output of latch 0 of the first 2-bit latch; drives 10 LSTTL loads (standard output). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HCT75M`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hct75m-etched.step` / `cd74hct75m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct75m.step` / `cd74hct75m.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct75) (19 pp, sha256 `215c79a298430f56`, retrieved 2026-10-05, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hct75m-datasheet.pdf)
page.jsonadded+208@@ -0,0 +1,208 @@+{+ "slug": "cd74hct75m",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hct75m",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hct75m.kicad_sym",+ "cd74hct75m.kicad_mod",+ "cd74hct75m.glb",+ "cd74hct75m.step",+ "cd74hct75m.lbr",+ "docs/hero.png",+ "docs/cd74hct75m-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd74hct75m-hero.glb",+ "cd74hct75m-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD74HCT75M",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct75",+ "parts": {+ "symbol": "cd74hct75m.kicad_sym",+ "footprint": "cd74hct75m.kicad_mod",+ "model_3d": "cd74hct75m-hero.glb",+ "model_3d_plain": "cd74hct75m.glb",+ "model_3d_step": "cd74hct75m-etched.step",+ "model_3d_step_plain": "cd74hct75m.step",+ "lbr": "cd74hct75m.lbr"+ },+ "distributor_links": {+ "lcsc": 1547800,+ "digikey": "296-26034-5-ND",+ "mouser": "595-CD74HCT75M"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T19:03:44Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-26034-5-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HCT75M",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1Q0̅",+ "type": "output",+ "description": "Complementary output of latch 0 of the first 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "2",+ "name": "1D0",+ "type": "input",+ "description": "Data input 0 of the first latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load)."+ },+ {+ "number": "3",+ "name": "1D1",+ "type": "input",+ "description": "Data input 1 of the first latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load)."+ },+ {+ "number": "4",+ "name": "2E",+ "type": "input",+ "description": "Enable input for the second 2-bit latch; data enters the latch and appears at Q when E is HIGH, output is not affected when LOW (1.2 unit loads)."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5V to 5.5V for HCT types (absolute maximum -0.5V to 7V)."+ },+ {+ "number": "6",+ "name": "2D0",+ "type": "input",+ "description": "Data input 0 of the second latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load)."+ },+ {+ "number": "7",+ "name": "2D1",+ "type": "input",+ "description": "Data input 1 of the second latch (HCT: VIH 2V min, VIL 0.8V max, 0.8 unit load)."+ },+ {+ "number": "8",+ "name": "2Q1̅",+ "type": "output",+ "description": "Complementary output of latch 1 of the second 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "9",+ "name": "2Q1",+ "type": "output",+ "description": "True output of latch 1 of the second 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "10",+ "name": "2Q0",+ "type": "output",+ "description": "True output of latch 0 of the second 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "11",+ "name": "2Q0̅",+ "type": "output",+ "description": "Complementary output of latch 0 of the second 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0V reference); DC VCC or ground current limit is ±50mA."+ },+ {+ "number": "13",+ "name": "1E",+ "type": "input",+ "description": "Enable input for the first 2-bit latch; data enters the latch and appears at Q when E is HIGH, output is not affected when LOW (1.2 unit loads)."+ },+ {+ "number": "14",+ "name": "1Q1̅",+ "type": "output",+ "description": "Complementary output of latch 1 of the first 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "15",+ "name": "1Q1",+ "type": "output",+ "description": "True output of latch 1 of the first 2-bit latch; drives 10 LSTTL loads (standard output)."+ },+ {+ "number": "16",+ "name": "1Q0",+ "type": "output",+ "description": "True output of latch 0 of the first 2-bit latch; drives 10 LSTTL loads (standard output)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout notation in datasheet shows duplicate signal names (1Q0, 1Q1, 2Q0, 2Q1 each appear on two pin"+ ],+ "pages_sent": 19,+ "cost_usd": 0.2048,+ "at": "2026-10-05T19:03:29"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct75",+ "pages": 19,+ "sha256": "215c79a298430f56",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}