component
CD74HCT73M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HCT73M96
Texas Instruments · Flip Flops · SOIC-14
CD74HCT73M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CP | input | Clock input of flip-flop 1, active on the negative-going (high-to-low) transition, with Schmitt-type hysteresis. |
| 2 | 1R | input | Active-low asynchronous reset input of flip-flop 1 that sets Q low and Q-bar high when held low. |
| 3 | 1K | input | K data input of flip-flop 1. |
| 4 | VCC | power_in | Positive supply; 4.5 V to 5.5 V for HCT types, bypassed with a 0.1-µF capacitor. |
| 5 | 2CP | input | Clock input of flip-flop 2, active on the negative-going (high-to-low) transition. |
| 6 | 2R | input | Active-low asynchronous reset input of flip-flop 2 that sets Q low and Q-bar high when held low. |
| 7 | 2J | input | J data input of flip-flop 2. |
| 8 | 2Q̅ | output | Complementary (inverted) output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2K | input | K data input of flip-flop 2. |
| 11 | GND | power_in | Ground reference. |
| 12 | 1Q | output | True output of flip-flop 1. |
| 13 | 1Q̅ | output | Complementary (inverted) output of flip-flop 1. |
| 14 | 1J | input | J data input of flip-flop 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage | VIH | 2 | V | VCC = 4.5 to 5.5 V, 25 °C | 5 | ||
| Low level input voltage | VIL | 0.8 | V | VCC = 4.5 to 5.5 V, 25 °C | 5 | ||
| High level output voltage | VOH | 4.4 | V | IOH = -20 μA, VCC = 4.5 V, 25 °C | 5 | ||
| High level output voltage | VOH | 3.98 | V | IOH = -4 mA, VCC = 4.5 V, 25 °C | 5 | ||
| High level output voltage | VOH | 3.84 | V | IOH = -4 mA, VCC = 4.5 V, -40 °C to 85 °C | 5 | ||
| High level output voltage | VOH | 3.7 | V | IOH = -4 mA, VCC = 4.5 V, -55 °C to 125 °C | 5 | ||
| Low level output voltage | VOL | 0.1 | V | IOL = 20 μA, VCC = 4.5 V, 25 °C | 5 | ||
| Low level output voltage | VOL | 0.26 | V | IOL = 4 mA, VCC = 4.5 V, 25 °C | 5 | ||
| Low level output voltage | VOL | 0.33 | V | IOL = 4 mA, VCC = 4.5 V, -40 °C to 85 °C | 5 | ||
| Low level output voltage | VOL | 0.4 | V | IOL = 4 mA, VCC = 4.5 V, -55 °C to 125 °C | 5 | ||
| Input leakage current | II | 0.1 | μA | VI = VCC and GND, VCC = 5.5 V, 25 °C | 5 | ||
| Input leakage current | II | 1 | μA | VI = VCC and GND, VCC = 5.5 V, -40 °C to 85 °C | 5 | ||
| Supply current | ICC | 4 | μA | VI = VCC and GND, VCC = 5.5 V, 25 °C | 5 | ||
| Supply current | ICC | 40 | μA | VI = VCC and GND, VCC = 5.5 V, -40 °C to 85 °C | 5 | ||
| Supply current | ICC | 80 | μA | VI = VCC and GND, VCC = 5.5 V, -55 °C to 125 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 100 | 108 | μA | All inputs held at VCC, 2.1 V, VCC = 4.5 to 5.5 V, 25 °C | 5 | |
| Additional supply current per input pin | ΔICC | 135 | μA | All inputs held at VCC, 2.1 V, VCC = 4.5 to 5.5 V, -40 °C to 85 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 147 | μA | All inputs held at VCC, 2.1 V, VCC = 4.5 to 5.5 V, -55 °C to 125 °C | 5 | ||
| CP pulse width | tw | 16 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 6 | ||
| CP pulse width | tw | 20 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 6 | ||
| CP pulse width | tw | 24 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 6 | ||
| R pulse width | tw | 18 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 6 | ||
| R pulse width | tw | 23 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 6 | ||
| R pulse width | tw | 27 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 6 | ||
| Setup time, J, K to CP | tSU | 16 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 6 | ||
| Setup time, J, K to CP | tSU | 20 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 6 | ||
| Setup time, J, K to CP | tSU | 24 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 6 | ||
| Removal time | tREM | 12 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 6 | ||
| Removal time | tREM | 15 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 6 | ||
| Removal time | tREM | 18 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 6 | ||
| CP frequency | fMAX | 30 | MHz | CL = 50 pF, VCC = 4.5 V, 25 °C | 6 | ||
| CP frequency | fMAX | 25 | MHz | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 6 | ||
| CP frequency | fMAX | 20 | MHz | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 6 | ||
| CP frequency | fMAX | 60 | MHz | CL = 15 pF, VCC = 5 V | 6 | ||
| Propagation delay, CP to Q | tPLH, tPHL | 38 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 7 | ||
| Propagation delay, CP to Q | tPLH, tPHL | 48 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 7 | ||
| Propagation delay, CP to Q | tPLH, tPHL | 57 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 7 | ||
| Propagation delay, R to Q, Q | tPLH, tPHL | 34 | ns | CL = 50 pF, VCC = 4.5 V, 25 °C | 7 | ||
| Propagation delay, R to Q, Q | tPLH, tPHL | 43 | ns | CL = 50 pF, VCC = 4.5 V, -40 °C to 85 °C | 7 | ||
| Propagation delay, R to Q, Q | tPLH, tPHL | 51 | ns | CL = 50 pF, VCC = 4.5 V, -55 °C to 125 °C | 7 | ||
| Supply voltage range, HCT types | VCC | 4.5 | 5.5 | V | HCT types | 4 | |
| Input rise and fall time | tt | 500 | ns | VCC = 4.5 V | 4 | ||
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input diode current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Drain current, per output | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | ICC | -50 | 50 | mA | 4 | ||
| Junction temperature | TJ | -150 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 138.7 | °C/W | D (SOIC) 14 pins | 4 |
CAD (KiCad official)
- Symbol:
CD74HCT73M96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hct73m96-etched.step/cd74hct73m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct73m96.step/cd74hct73m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
2cdd29cf8fbc3b52, retrieved 2026-10-17, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).