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CD74HCT73E

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Texas Instruments Flip Flops, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT73E

Texas Instruments · Flip Flops · PDIP-14

CD74HCT73E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input of flip-flop 1, active on the negative-going (high-to-low) transition, with Schmitt-type hysteresis.
2 1R input Asynchronous active-low reset input of flip-flop 1; a low level forces Q low and Q-bar high.
3 1K input K data input of flip-flop 1, sampled on the falling clock edge.
4 VCC power_in Positive supply; HCT types operate from 4.5 V to 5.5 V, with a 0.1-uF bypass capacitor recommended.
5 2CP input Clock input of flip-flop 2, active on the negative-going (high-to-low) transition, with Schmitt-type hysteresis.
6 2R input Asynchronous active-low reset input of flip-flop 2; a low level forces Q low and Q-bar high.
7 2J input J data input of flip-flop 2, sampled on the falling clock edge.
8 2Q̅ output Complementary (inverted) output of flip-flop 2.
9 2Q output True output of flip-flop 2.
10 2K input K data input of flip-flop 2, sampled on the falling clock edge.
11 GND power_in Ground reference (0 V).
12 1Q output True output of flip-flop 1.
13 1Q̅ output Complementary (inverted) output of flip-flop 1.
14 1J input J data input of flip-flop 1, sampled on the falling clock edge.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input diode current IIK -20 20 mA For VI < -0.5 V or VI > VCC + 0.5 V 4
Drain current, per output IO -25 25 mA For -0.5 V < VO < VCC + 0.5 V 4
Output diode current IOK -20 20 mA For VO < -0.5 V or VO > VCC + 0.5 V 4
Output source or sink current per output pin IO -25 25 mA For VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND ICC -50 50 mA 4
Junction temperature TJ -150 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage range, HCT types VCC 4.5 5.5 V HCT types 4
Input or output voltage VI, VO 0 V Maximum is VCC as printed 4
Input rise and fall time tt 500 ns VCC = 4.5 V 4
Temperature range TA -55 125 °C 4
Junction-to-ambient thermal resistance RθJA 91 °C/W N (PDIP) 14-pin package 4
Junction-to-case (top) thermal resistance RθJC(top) 78.9 °C/W N (PDIP) 14-pin package 4
Junction-to-board thermal resistance RθJB 70.7 °C/W N (PDIP) 14-pin package 4
Junction-to-top characterization parameter ψJT 58.6 °C/W N (PDIP) 14-pin package 4
Junction-to-board characterization parameter ψJB 70.5 °C/W N (PDIP) 14-pin package 4
High level input voltage VIH 2 V HCT types, VCC 4.5 to 5.5 V, -55 to 125 °C 5
Low level input voltage VIL 0.8 V HCT types, VCC 4.5 to 5.5 V, -55 to 125 °C 5
High level output voltage VOH 4.4 V IOH = -20 μA, VCC 4.5 V, -55 to 125 °C 5
High level output voltage VOH 3.7 V IOH = -4 mA, VCC 4.5 V, -55 to 125 °C 5
Low level output voltage VOL 0.1 V IOL = 20 μA, VCC 4.5 V, -55 to 125 °C 5
Low level output voltage VOL 0.4 V IOL = 4 mA, VCC 4.5 V, -55 to 125 °C 5
Input leakage current II -1 1 μA VI = VCC and GND, VCC 5.5 V, -55 to 125 °C 5
Supply current ICC 80 μA VI = VCC and GND, VCC 5.5 V, -55 to 125 °C 5
Additional supply current per input pin ΔICC 147 μA All inputs held at VCC - 2.1 V, VCC 4.5 to 5.5 V, -55 to 125 °C 5
CP pulse width tw 24 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
R pulse width tw 27 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
Setup time, J, K to CP tSU 24 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
Hold time, J, K to CP tH 3 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
Removal time tREM 18 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
CP frequency fMAX 20 MHz CL = 50 pF, VCC 4.5 V, -55 to 125 °C 6
Propagation delay, CP to Q tPLH, tPHL 57 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 7
Propagation delay, CP to Q tPLH, tPHL 54 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 7
Propagation delay, R to Q, Q tPLH, tPHL 51 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 7
Output transition time tTLH, tTHL 22 ns CL = 50 pF, VCC 4.5 V, -55 to 125 °C 7

CAD (KiCad official)

  • Symbol: CD74HCT73E
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hct73e-etched.step / cd74hct73e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct73e.step / cd74hct73e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 2cdd29cf8fbc3b52, retrieved 2026-11-07, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF