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Generated by kicad-footprint-generator · KiCad file format 20260206

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cd74hct574pwr-etched.glb	cd74hct574pwr: factory component page (tier=mfr) · Ray	2d ago
cd74hct574pwr-etched.step	cd74hct574pwr: factory component page (tier=mfr) · Ray	2d ago
cd74hct574pwr-hero.glb	cd74hct574pwr: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
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README.md	Initial commit: component/cd74hct574pwr · Ray	2d ago

CD74HCT574PWR

Texas Instruments · Flip Flops · TSSOP-20

CD74HCT574PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Active-low output enable; when HIGH the Q outputs are in the high-impedance state, independent of register operation.
2	D0	input	Data input 0, latched on the LOW-to-HIGH transition of CP.
3	D1	input	Data input 1, latched on the LOW-to-HIGH transition of CP.
4	D2	input	Data input 2, latched on the LOW-to-HIGH transition of CP.
5	D3	input	Data input 3, latched on the LOW-to-HIGH transition of CP.
6	D4	input	Data input 4, latched on the LOW-to-HIGH transition of CP.
7	D5	input	Data input 5, latched on the LOW-to-HIGH transition of CP.
8	D6	input	Data input 6, latched on the LOW-to-HIGH transition of CP.
9	D7	input	Data input 7, latched on the LOW-to-HIGH transition of CP.
10	GND	power_in	Ground.
11	CP	input	Clock input; data is entered into the registers on the LOW-to-HIGH transition.
12	Q7	tri_state	3-state flip-flop output 7, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
13	Q6	tri_state	3-state flip-flop output 6, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
14	Q5	tri_state	3-state flip-flop output 5, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
15	Q4	tri_state	3-state flip-flop output 4, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
16	Q3	tri_state	3-state flip-flop output 3, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
17	Q2	tri_state	3-state flip-flop output 2, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
18	Q1	tri_state	3-state flip-flop output 1, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
19	Q0	tri_state	3-state flip-flop output 0, high-impedance when OE is HIGH; drives up to 15 LSTTL loads.
20	VCC	power_in	Supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: CD74HCT574PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: cd74hct574pwr-etched.step / cd74hct574pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct574pwr.step / cd74hct574pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (27 pp, sha256 fca1397379cec05b, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF