component
CD74HCT573M96
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"cd74hct573m96.step",
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"component": {
"mpn": "CD74HCT573M96",
"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
"category": "Logic",
"subcategory": "Latches",
"datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct573",
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"lbr": "cd74hct573m96.lbr"
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"distributor_links": {
"lcsc": "C2863738",
"digikey": "296-9291-2-ND",
"mouser": "595-CD74HCT573M96"
},
"distributor_check": {
"checked_at": "2026-10-08T20:16:28Z",
"source": "Component Ocean /api/assign-pns",
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"pn": "296-9291-2-ND",
"status": "found",
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"pn": "595-CD74HCT573M96",
"status": "found"
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},
"pins": [
{
"number": "1",
"name": "OE",
"type": "input",
"description": "Active-low output enable; high places the eight Q outputs in the high-impedance state without affecting the latches, and should be tied to VCC through a pullup resistor during power up or down."
},
{
"number": "2",
"name": "1D",
"type": "input",
"description": "Data input 1 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "3",
"name": "2D",
"type": "input",
"description": "Data input 2 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "4",
"name": "3D",
"type": "input",
"description": "Data input 3 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "5",
"name": "4D",
"type": "input",
"description": "Data input 4 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "6",
"name": "5D",
"type": "input",
"description": "Data input 5 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "7",
"name": "6D",
"type": "input",
"description": "Data input 6 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "8",
"name": "7D",
"type": "input",
"description": "Data input 7 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "9",
"name": "8D",
"type": "input",
"description": "Data input 8 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Ground reference; continuous current through VCC or GND is limited to ±50 mA."
},
{
"number": "11",
"name": "LE",
"type": "input",
"description": "Latch enable; Q outputs follow D when high and are latched at the D logic levels when low."
},
{
"number": "12",
"name": "8Q",
"type": "tri_state",
"description": "Three-state latch output 8, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "13",
"name": "7Q",
"type": "tri_state",
"description": "Three-state latch output 7, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "14",
"name": "6Q",
"type": "tri_state",
"description": "Three-state latch output 6, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "15",
"name": "5Q",
"type": "tri_state",
"description": "Three-state latch output 5, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "16",
"name": "4Q",
"type": "tri_state",
"description": "Three-state latch output 4, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "17",
"name": "3Q",
"type": "tri_state",
"description": "Three-state latch output 3, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "18",
"name": "2Q",
"type": "tri_state",
"description": "Three-state latch output 2, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "19",
"name": "1Q",
"type": "tri_state",
"description": "Three-state latch output 1, high-impedance when OE is high, with ±25 mA maximum continuous output current."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 7 V), with a 0.1-µF bypass capacitor recommended close to the pin."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text+vision",
"consensus_model": "claude-opus-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The ordering table lists CD74HCT573M96 as SOIC (DW) 20-pin (DW0020A, 7.5 mm body, MS-013). The packa",
"vision extraction: provenance cannot be text-verified; needs consensus"
],
"pages_sent": 23,
"cost_usd": 0.4339,
"at": "2026-10-08T20:15:46"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/cd74hct573",
"pages": 23,
"sha256": "406bb2e4f31d849d",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 20,
"described": 20,
"cites_pages": true,
"refuses_to_fabricate": true
}
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{
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