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CD74HCT573M96

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT573M96

Texas Instruments · Latches · SOIC-20-300mil

CD74HCT573M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable; high places the eight Q outputs in the high-impedance state without affecting the latches, and should be tied to VCC through a pullup resistor during power up or down.
2 1D input Data input 1 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
3 2D input Data input 2 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
4 3D input Data input 3 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
5 4D input Data input 4 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
6 5D input Data input 5 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
7 6D input Data input 6 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
8 7D input Data input 7 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
9 8D input Data input 8 (TTL-compatible, VIH min 2 V, VIL max 0.8 V); Q follows D while LE is high.
10 GND power_in Ground reference; continuous current through VCC or GND is limited to ±50 mA.
11 LE input Latch enable; Q outputs follow D when high and are latched at the D logic levels when low.
12 8Q tri_state Three-state latch output 8, high-impedance when OE is high, with ±25 mA maximum continuous output current.
13 7Q tri_state Three-state latch output 7, high-impedance when OE is high, with ±25 mA maximum continuous output current.
14 6Q tri_state Three-state latch output 6, high-impedance when OE is high, with ±25 mA maximum continuous output current.
15 5Q tri_state Three-state latch output 5, high-impedance when OE is high, with ±25 mA maximum continuous output current.
16 4Q tri_state Three-state latch output 4, high-impedance when OE is high, with ±25 mA maximum continuous output current.
17 3Q tri_state Three-state latch output 3, high-impedance when OE is high, with ±25 mA maximum continuous output current.
18 2Q tri_state Three-state latch output 2, high-impedance when OE is high, with ±25 mA maximum continuous output current.
19 1Q tri_state Three-state latch output 1, high-impedance when OE is high, with ±25 mA maximum continuous output current.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 7 V), with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74HCT573M96
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74hct573m96-etched.step / cd74hct573m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct573m96.step / cd74hct573m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 406bb2e4f31d849d, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF