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CD74HCT4052M
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Texas Instruments Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74HCT4052M++**Texas Instruments** · Analog Switches, Multiplexers · SOIC-16++CD74HCT4052M from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CH B0 | bidirectional | Channel B0 analog input/output of the B switch bank, which passes analog signals between VEE and VCC when enabled. |+| 2 | CH B2 | bidirectional | Channel B2 analog input/output of the B switch bank, which passes analog signals between VEE and VCC when enabled. |+| 3 | COM B | bidirectional | Common B analog output/input that connects to the selected B channel, with analog switch voltage limited to VEE to VCC. |+| 4 | CH B3 | bidirectional | Channel B3 analog input/output of the B switch bank, which passes analog signals between VEE and VCC when enabled. |+| 5 | CH B1 | bidirectional | Channel B1 analog input/output of the B switch bank, which passes analog signals between VEE and VCC when enabled. |+| 6 | E | input | Active-low enable input; when driven high all switches are disabled to the off state, and control inputs must stay within 0 V to VCC. |+| 7 | VEE | power_in | Negative power supply input; the datasheet specifies VEE from 0 V to -6 V and VCC - VEE from 2 V to 10 V. |+| 8 | GND | power_in | Ground reference for all voltages; the datasheet states that all voltages are referenced to GND unless otherwise noted. |+| 9 | S1 | input | Channel select 1 control input, which together with S0 selects the active channel; logic levels are referenced to GND with VIH minimum 2 V and VIL maximum 0.8 V at 4.5 V to 5.5 V VCC. |+| 10 | S0 | input | Channel select 0 control input, which together with S1 selects the active channel; logic levels are referenced to GND with VIH minimum 2 V and VIL maximum 0.8 V at 4.5 V to 5.5 V VCC. |+| 11 | CH A3 | bidirectional | Channel A3 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled. |+| 12 | CH A0 | bidirectional | Channel A0 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled. |+| 13 | COM A | bidirectional | Common A analog input/output that connects to the selected A channel, with analog switch voltage limited to VEE to VCC. |+| 14 | CH A1 | bidirectional | Channel A1 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled. |+| 15 | CH A2 | bidirectional | Channel A2 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled. |+| 16 | VCC | power_in | Positive power supply input; the datasheet specifies VCC from 2 V to 6 V (HC) and 4.5 V to 5.5 V (HCT), with VCC - VEE up to 10 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Interface |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HCT4052M`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hct4052m-etched.step` / `cd74hct4052m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct4052m.step` / `cd74hct4052m.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct4051) (50 pp, sha256 `cc5bd993625a4388`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hct4052m-datasheet.pdf)
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when driven high all switches are disabled to the off state, and control inputs must stay within 0 V to VCC."+ },+ {+ "number": "7",+ "name": "VEE",+ "type": "power_in",+ "description": "Negative power supply input; the datasheet specifies VEE from 0 V to -6 V and VCC - VEE from 2 V to 10 V."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for all voltages; the datasheet states that all voltages are referenced to GND unless otherwise noted."+ },+ {+ "number": "9",+ "name": "S1",+ "type": "input",+ "description": "Channel select 1 control input, which together with S0 selects the active channel; logic levels are referenced to GND with VIH minimum 2 V and VIL maximum 0.8 V at 4.5 V to 5.5 V VCC."+ },+ {+ "number": "10",+ "name": "S0",+ "type": "input",+ "description": "Channel select 0 control input, which together with S1 selects the active channel; logic levels are referenced to GND with VIH minimum 2 V and VIL maximum 0.8 V at 4.5 V to 5.5 V VCC."+ },+ {+ "number": "11",+ "name": "CH A3",+ "type": "bidirectional",+ "description": "Channel A3 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled."+ },+ {+ "number": "12",+ "name": "CH A0",+ "type": "bidirectional",+ "description": "Channel A0 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled."+ },+ {+ "number": "13",+ "name": "COM A",+ "type": "bidirectional",+ "description": "Common A analog input/output that connects to the selected A channel, with analog switch voltage limited to VEE to VCC."+ },+ {+ "number": "14",+ "name": "CH A1",+ "type": "bidirectional",+ "description": "Channel A1 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled."+ },+ {+ "number": "15",+ "name": "CH A2",+ "type": "bidirectional",+ "description": "Channel A2 analog input/output of the A switch bank, which passes analog signals between VEE and VCC when enabled."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive power supply input; the datasheet specifies VCC from 2 V to 6 V (HC) and 4.5 V to 5.5 V (HCT), with VCC - VEE up to 10 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's pinout covers the CD74HCT4052 in the D (SOIC, 16) package. Pin numbers are taken fro; Page 33 of the package addendum lists CD74HCT4052M as Obsolete. The active SOIC orderable is CD74HCT; Pin types for the channel and common pins are mapped from the datasheet's I/O label to KiCad bidirec"+ ],+ "pages_sent": 22,+ "cost_usd": 0.1298,+ "at": "2026-10-08T20:41:48"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct4051",+ "pages": 50,+ "sha256": "cc5bd993625a4388",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hct4052m.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hct4052m-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "969fa13a685febc4d701a4718607b69576828c7f9cfb4c7b9a0c473ed9785a3e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}