component
CD74HCT4040M96
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "CD74HCT4040M96",
"manufacturer": "Texas Instruments",
"package": "SOIC-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Counters, Dividers",
"datasheet": "https://www.ti.com/lit/ds/symlink/cd74hct4040m96.pdf",
"parts": {
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"distributor_links": {
"lcsc": "C2865249",
"digikey": "296-14558-2-ND",
"mouser": "595-CD74HCT4040M96"
},
"distributor_check": {
"checked_at": "2026-10-18T05:41:50Z",
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},
"pins": [
{
"number": "1",
"name": "Q12",
"type": "output",
"description": "Counter stage 12 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "2",
"name": "Q6",
"type": "output",
"description": "Counter stage 6 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "3",
"name": "Q5",
"type": "output",
"description": "Counter stage 5 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "4",
"name": "Q7",
"type": "output",
"description": "Counter stage 7 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "5",
"name": "Q4",
"type": "output",
"description": "Counter stage 4 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "6",
"name": "Q3",
"type": "output",
"description": "Counter stage 3 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "7",
"name": "Q2",
"type": "output",
"description": "Counter stage 2 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground, 0 V reference."
},
{
"number": "9",
"name": "Q1'",
"type": "output",
"description": "Counter stage 1 output (CP to Q1' path), buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "10",
"name": "CP",
"type": "input",
"description": "Clock pulse input, buffered; counter advances on each negative (high-to-low) clock transition, HCT max input frequency 25 MHz at 4.5 V."
},
{
"number": "11",
"name": "MR",
"type": "input",
"description": "Master reset input; a high level resets all counter stages so all outputs go low."
},
{
"number": "12",
"name": "Q9",
"type": "output",
"description": "Counter stage 9 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "13",
"name": "Q8",
"type": "output",
"description": "Counter stage 8 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "14",
"name": "Q10",
"type": "output",
"description": "Counter stage 10 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "15",
"name": "Q11",
"type": "output",
"description": "Counter stage 11 output, buffered, drives up to 10 LSTTL loads (standard output)."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply; HCT types operate from 4.5 V to 5.5 V, with a 0.1-µF bypass capacitor recommended close to the pin."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"primary_model": "claude-sonnet-5-5",
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"consensus_model": "claude-opus-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
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"vision extraction: provenance cannot be text-verified; needs consensus"
],
"pages_sent": 23,
"cost_usd": 0.397,
"at": "2026-10-18T05:40:37"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/cd74hct4040m96.pdf",
"pages": 23,
"sha256": "85aaba4669d66cf5",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
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"described": 16,
"cites_pages": true,
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}
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