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CD74HCT4040M96
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HCT4040M96
Texas Instruments · Counters, Dividers · SOIC-16
CD74HCT4040M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Counter stage 12 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 2 | Q6 | output | Counter stage 6 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 3 | Q5 | output | Counter stage 5 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 4 | Q7 | output | Counter stage 7 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 5 | Q4 | output | Counter stage 4 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 6 | Q3 | output | Counter stage 3 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 7 | Q2 | output | Counter stage 2 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 8 | GND | power_in | Ground, 0 V reference. |
| 9 | Q1' | output | Counter stage 1 output (CP to Q1' path), buffered, drives up to 10 LSTTL loads (standard output). |
| 10 | CP | input | Clock pulse input, buffered; counter advances on each negative (high-to-low) clock transition, HCT max input frequency 25 MHz at 4.5 V. |
| 11 | MR | input | Master reset input; a high level resets all counter stages so all outputs go low. |
| 12 | Q9 | output | Counter stage 9 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 13 | Q8 | output | Counter stage 8 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 14 | Q10 | output | Counter stage 10 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 15 | Q11 | output | Counter stage 11 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 16 | VCC | power_in | Positive supply; HCT types operate from 4.5 V to 5.5 V, with a 0.1-µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage (HCT), VCC 4.5 to 5.5 V | VIH | 2 | V | VCC 4.5 V to 5.5 V; -55 to 125 °C column | 5 | ||
| Low level input voltage (HCT), VCC 4.5 to 5.5 V | VIL | 0.8 | V | VCC 4.5 V to 5.5 V; -55 to 125 °C column | 5 | ||
| High level output voltage, CMOS loads | VOH | 4.4 | V | IOH = -20 µA, VCC 4.5 V; -55 to 125 °C column | 5 | ||
| High level output voltage, TTL loads | VOH | 3.7 | V | IOH = -4 mA, VCC 4.5 V; -55 to 125 °C column | 5 | ||
| Low level output voltage, CMOS loads | VOL | 0.1 | V | IOL = 20 µA, VCC 4.5 V; -55 to 125 °C column | 5 | ||
| Low level output voltage, TTL loads | VOL | 0.4 | V | IOL = 4 mA, VCC 4.5 V; -55 to 125 °C column | 5 | ||
| Input leakage current | II | -1 | 1 | µA | VCC and GND, VCC 5.5 V; -55 to 125 °C column | 5 | |
| Supply current | ICC | 160 | µA | VCC or GND, VCC 5.5 V; -55 to 125 °C column | 5 | ||
| Additional supply current per input pin, MR input | ΔICC | 100 | 318.5 | µA | MR input held at VCC - 2.1 V, VCC 4.5 to 5.5 V; -55 to 125 °C column (typ at 25 °C) | 5 | |
| Additional supply current per input pin, CP input | ΔICC | 100 | 245 | µA | CP input held at VCC - 2.1 V, VCC 4.5 to 5.5 V; -55 to 125 °C column (typ at 25 °C) | 5 | |
| Supply voltage range, HCT types | VCC | 4.5 | 5.5 | V | HCT types | 4 | |
| DC input or output voltage | VI, VO | 0 | V | Maximum is VCC | 4 | ||
| Input rise and fall time | tr, tf | 500 | ns | VCC 4.5 V | 4 | ||
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output source or sink current per output pin | IO | -25 | 25 | mA | VO > -0.5 V or VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance, D (SOIC) 16 pins | RθJA | 73 | °C/W | D (SOIC) package, 16 pins | 4 | ||
| Maximum input pulse frequency, HCT | fMAX | 16 | MHz | VCC 4.5 V; -55 to 125 °C column | 6 | ||
| Input pulse width, HCT | tW | 30 | ns | VCC 4.5 V; -55 to 125 °C column | 6 | ||
| Reset recovery time, HCT | tREC | 15 | ns | VCC 4.5 V; -55 to 125 °C column | 6 | ||
| Reset pulse width, HCT | tW | 30 | ns | VCC 4.5 V; -55 to 125 °C column | 6 | ||
| Propagation delay time CP to Q1' output | tPLH, tPHL | 60 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 | ||
| Propagation delay time CP to Q1' output | tPLH, tPHL | 17 | ns | CL = 15 pF, VCC 5 V | 7 | ||
| Propagation delay time Qn to Qn+1 | tPLH, tPHL | 22 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 | ||
| Propagation delay time Qn to Qn+1 | tPLH, tPHL | 4 | ns | CL = 15 pF, VCC 5 V | 7 | ||
| Propagation delay time MR to Qn | tPLH, tPHL | 60 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 | ||
| Propagation delay time MR to Qn | tPLH, tPHL | 17 | ns | CL = 15 pF, VCC 5 V | 7 | ||
| Output transition time | tTLH, tTHL | 22 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 | ||
| Input capacitance | CIN | 10 | pF | CL = 50 pF | 7 |
CAD (KiCad official)
- Symbol:
CD74HCT4040M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hct4040m96-etched.step/cd74hct4040m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct4040m96.step/cd74hct4040m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
85aaba4669d66cf5, retrieved 2026-10-18, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HCT4040M96
**Texas Instruments** · Counters, Dividers · SOIC-16
CD74HCT4040M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Counter stage 12 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 2 | Q6 | output | Counter stage 6 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 3 | Q5 | output | Counter stage 5 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 4 | Q7 | output | Counter stage 7 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 5 | Q4 | output | Counter stage 4 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 6 | Q3 | output | Counter stage 3 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 7 | Q2 | output | Counter stage 2 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 8 | GND | power_in | Ground, 0 V reference. |
| 9 | Q1' | output | Counter stage 1 output (CP to Q1' path), buffered, drives up to 10 LSTTL loads (standard output). |
| 10 | CP | input | Clock pulse input, buffered; counter advances on each negative (high-to-low) clock transition, HCT max input frequency 25 MHz at 4.5 V. |
| 11 | MR | input | Master reset input; a high level resets all counter stages so all outputs go low. |
| 12 | Q9 | output | Counter stage 9 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 13 | Q8 | output | Counter stage 8 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 14 | Q10 | output | Counter stage 10 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 15 | Q11 | output | Counter stage 11 output, buffered, drives up to 10 LSTTL loads (standard output). |
| 16 | VCC | power_in | Positive supply; HCT types operate from 4.5 V to 5.5 V, with a 0.1-µF bypass capacitor recommended close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage (HCT), VCC 4.5 to 5.5 V | VIH | 2 | | | V | VCC 4.5 V to 5.5 V; -55 to 125 °C column | 5 |
| Low level input voltage (HCT), VCC 4.5 to 5.5 V | VIL | | | 0.8 | V | VCC 4.5 V to 5.5 V; -55 to 125 °C column | 5 |
| High level output voltage, CMOS loads | VOH | 4.4 | | | V | IOH = -20 µA, VCC 4.5 V; -55 to 125 °C column | 5 |
| High level output voltage, TTL loads | VOH | 3.7 | | | V | IOH = -4 mA, VCC 4.5 V; -55 to 125 °C column | 5 |
| Low level output voltage, CMOS loads | VOL | | | 0.1 | V | IOL = 20 µA, VCC 4.5 V; -55 to 125 °C column | 5 |
| Low level output voltage, TTL loads | VOL | | | 0.4 | V | IOL = 4 mA, VCC 4.5 V; -55 to 125 °C column | 5 |
| Input leakage current | II | -1 | | 1 | µA | VCC and GND, VCC 5.5 V; -55 to 125 °C column | 5 |
| Supply current | ICC | | | 160 | µA | VCC or GND, VCC 5.5 V; -55 to 125 °C column | 5 |
| Additional supply current per input pin, MR input | ΔICC | | 100 | 318.5 | µA | MR input held at VCC - 2.1 V, VCC 4.5 to 5.5 V; -55 to 125 °C column (typ at 25 °C) | 5 |
| Additional supply current per input pin, CP input | ΔICC | | 100 | 245 | µA | CP input held at VCC - 2.1 V, VCC 4.5 to 5.5 V; -55 to 125 °C column (typ at 25 °C) | 5 |
| Supply voltage range, HCT types | VCC | 4.5 | | 5.5 | V | HCT types | 4 |
| DC input or output voltage | VI, VO | 0 | | | V | Maximum is VCC | 4 |
| Input rise and fall time | tr, tf | | | 500 | ns | VCC 4.5 V | 4 |
| Temperature range | TA | -55 | | 125 | °C | | 4 |
| Supply voltage range | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Output source or sink current per output pin | IO | -25 | | 25 | mA | VO > -0.5 V or VCC + 0.5 V | 4 |
| Continuous current through VCC or GND | | -50 | | 50 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Junction-to-ambient thermal resistance, D (SOIC) 16 pins | RθJA | | 73 | | °C/W | D (SOIC) package, 16 pins | 4 |
| Maximum input pulse frequency, HCT | fMAX | 16 | | | MHz | VCC 4.5 V; -55 to 125 °C column | 6 |
| Input pulse width, HCT | tW | 30 | | | ns | VCC 4.5 V; -55 to 125 °C column | 6 |
| Reset recovery time, HCT | tREC | 15 | | | ns | VCC 4.5 V; -55 to 125 °C column | 6 |
| Reset pulse width, HCT | tW | 30 | | | ns | VCC 4.5 V; -55 to 125 °C column | 6 |
| Propagation delay time CP to Q1' output | tPLH, tPHL | | | 60 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 |
| Propagation delay time CP to Q1' output | tPLH, tPHL | | | 17 | ns | CL = 15 pF, VCC 5 V | 7 |
| Propagation delay time Qn to Qn+1 | tPLH, tPHL | | | 22 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 |
| Propagation delay time Qn to Qn+1 | tPLH, tPHL | | | 4 | ns | CL = 15 pF, VCC 5 V | 7 |
| Propagation delay time MR to Qn | tPLH, tPHL | | | 60 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 |
| Propagation delay time MR to Qn | tPLH, tPHL | | | 17 | ns | CL = 15 pF, VCC 5 V | 7 |
| Output transition time | tTLH, tTHL | | | 22 | ns | CL = 50 pF, VCC 4.5 V; -55 to 125 °C column | 7 |
| Input capacitance | CIN | | | 10 | pF | CL = 50 pF | 7 |
## CAD (KiCad official)
- Symbol: `CD74HCT4040M96`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `cd74hct4040m96-etched.step` / `cd74hct4040m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct4040m96.step` / `cd74hct4040m96.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hct4040m96.pdf) (23 pp, sha256 `85aaba4669d66cf5`, retrieved 2026-10-18, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hct4040m96-datasheet.pdf)