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CD74HCT4024E
Public Made by Adomby adom
Texas Instruments Counters, Dividers, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HCT4024E
Texas Instruments · Counters, Dividers · PDIP-14
CD74HCT4024E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP | input | Clock input, buffered, advancing the counter one count on each negative (high-to-low) transition. |
| 2 | MR | input | Master reset input, buffered; a high level resets all counter stages to zero and drives all outputs low. |
| 3 | Q7 | output | Buffered counter stage 7 output. |
| 4 | Q6 | output | Buffered counter stage 6 output. |
| 5 | Q5 | output | Buffered counter stage 5 output. |
| 6 | Q4 | output | Buffered counter stage 4 output. |
| 7 | GND | power_in | Ground pin (0 V reference). |
| 8 | NC | unconnected | No internal connection. |
| 9 | Q3 | output | Buffered counter stage 3 output. |
| 10 | NC | unconnected | No internal connection. |
| 11 | Q2 | output | Buffered counter stage 2 output. |
| 12 | Q1' | output | Buffered counter stage 1 output (Q1'). |
| 13 | NC | unconnected | No internal connection. |
| 14 | VCC | power_in | Positive supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1-µF bypass capacitor recommended. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input diode current | IIK | -20 | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output diode current | IOK | -20 | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output source or sink current per output pin | IO | -25 | 25 | mA | For VO > -0.5 V or VO < VCC+ 0.5 V | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | ℃ | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 4 | ||
| Supply voltage range, HCT types | VCC | 4.5 | 5.5 | V | HCT types | 4 | |
| DC input or output voltage | VI, VO | 0 | V | Upper limit printed as VCC | 4 | ||
| Input rise and fall time | tt | 500 | ns | VCC = 4.5 V | 4 | ||
| Temperature range | TA | -55 | 125 | ℃ | 4 | ||
| High level input voltage | VIH | 2 | V | VCC 4.5 to 5.5 V | 5 | ||
| Low level input voltage | VIL | 0.8 | V | VCC 4.5 to 5.5 V | 5 | ||
| High level output voltage, CMOS loads | VOH | 4.4 | V | IOH =, 20 μA, VCC 4.5 V, CMOS loads | 5 | ||
| High level output voltage, TTL loads | VOH | 3.7 | V | IOH =, 4 mA, VCC 4.5 V, TTL loads, -55℃ to 125℃ | 5 | ||
| Low level output voltage, CMOS loads | VOL | 0.1 | V | IOL = 20 μA, VCC 4.5 V | 5 | ||
| Low level output voltage, TTL loads | VOL | 0.4 | V | IOL = 4 mA, VCC 4.5 V, -55℃ to 125℃ | 5 | ||
| Input leakage current | II | -1 | 1 | μA | VCC and GND, VCC 5.5 V, -55℃ to 125℃ | 5 | |
| Supply current | ICC | 160 | μA | VCC or GND, VCC 5.5 V, -55℃ to 125℃ | 5 | ||
| Additional supply current per input pin | ΔICC | 100 | 245 | μA | CP, MR inputs held at VCC - 2.1, VCC 4.5 to 5.5 V, -55℃ to 125℃; typ at 25℃ | 5 | |
| Additional supply current per input pin, dual-supply worst case | ΔICC | 1.8 | mA | Dual-supply systems theoretical worst case, VI = 2.4 V, VCC = 5.5 V | 5 | ||
| Maximum input pulse frequency | fMAX | 16 | MHz | VCC 4.5 V, -55℃ to 125℃ | 6 | ||
| Input pulse width | tW | 30 | ns | VCC 4.5 V, -55℃ to 125℃ | 6 | ||
| Reset recovery time | tREC | 15 | ns | VCC 4.5 V, -55℃ to 125℃ | 6 | ||
| Reset pulse width | tW | 30 | ns | VCC 4.5 V, -55℃ to 125℃ | 6 | ||
| Propagation delay time, CP to Q1' output | tPLH, tPHL | 40 | 60 | ns | CL = 50 pF, VCC 4.5 V, tr, tf = 6 ns, -55℃ to 125℃; typ at 25℃ | 7 | |
| Propagation delay time, Qn to Qn + 1 | tPLH, tPHL | 15 | 22 | ns | CL = 50 pF, VCC 4.5 V, tr, tf = 6 ns, -55℃ to 125℃; typ at 25℃ | 7 | |
| Propagation delay time, MR to Qn | tPLH, tPHL | 40 | 60 | ns | CL = 50 pF, VCC 4.5 V, tr, tf = 6 ns, -55℃ to 125℃; typ at 25℃ | 7 | |
| Output transition time | tTLH, tTHL | 15 | 22 | ns | CL = 50 pF, VCC 4.5 V, tr, tf = 6 ns, -55℃ to 125℃; typ at 25℃ | 7 | |
| Input capacitance | CIN | 10 | 10 | pF | CL = 15 pF, -55℃ to 125℃; typ at 25℃ | 7 | |
| Junction-to-ambient thermal resistance, N (PDIP) 14-pin | RθJA | 80 | °C/W | N (PDIP) package, 14 pins; single printed value | 4 |
CAD (KiCad official)
- Symbol:
CD74HCT4024E - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hct4024e-etched.step/cd74hct4024e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct4024e.step/cd74hct4024e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
905707e958030bfa, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).