component
CD74HCT377M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"slug": "cd74hct377m96",
"title": "CD74HCT377M96",
"brief": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
"category": "Logic",
"subcategory": "Flip Flops",
"datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct377",
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"digikey": "296-38703-2-ND",
"mouser": "595-CD74HCT377M96"
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"pins": [
{
"number": "1",
"name": "E",
"type": "input",
"description": "Active-low data enable input common to all eight flip-flops; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns before rising CP edge at VCC=4.5 V; presents 1.5 HCT unit loads (≤360 µA each at 25 °C)."
},
{
"number": "2",
"name": "Q0",
"type": "output",
"description": "Registered Q output of flip-flop 0; assumes state of D0 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; propagation delay tPHL/tPLH ≤38 ns at CL=50 pF, VCC=4.5 V."
},
{
"number": "3",
"name": "D0",
"type": "input",
"description": "Data input for flip-flop 0; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."
},
{
"number": "4",
"name": "D1",
"type": "input",
"description": "Data input for flip-flop 1; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."
},
{
"number": "5",
"name": "Q1",
"type": "output",
"description": "Registered Q output of flip-flop 1; assumes state of D1 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
},
{
"number": "6",
"name": "Q2",
"type": "output",
"description": "Registered Q output of flip-flop 2; assumes state of D2 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF."
},
{
"number": "7",
"name": "D2",
"type": "input",
"description": "Data input for flip-flop 2; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."
},
{
"number": "8",
"name": "D3",
"type": "input",
"description": "Data input for flip-flop 3; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
},
{
"number": "9",
"name": "Q3",
"type": "output",
"description": "Registered Q output of flip-flop 3; assumes state of D3 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Ground supply reference for all internal logic; DC GND current ICC/IGND must not exceed ±50 mA absolute maximum."
},
{
"number": "11",
"name": "CP",
"type": "input",
"description": "Buffered clock input common to all eight flip-flops; flip-flops load on rising edge when E is Low; maximum clock frequency 25 MHz at VCC=4.5 V; clock pulse width tW ≥20 ns at VCC=4.5 V; presents 0.5 HCT unit loads."
},
{
"number": "12",
"name": "Q7",
"type": "output",
"description": "Registered Q output of flip-flop 7; assumes state of D7 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
},
{
"number": "13",
"name": "D7",
"type": "input",
"description": "Data input for flip-flop 7; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."
},
{
"number": "14",
"name": "D4",
"type": "input",
"description": "Data input for flip-flop 4; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
},
{
"number": "15",
"name": "Q4",
"type": "output",
"description": "Registered Q output of flip-flop 4; assumes state of D4 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL ≤38 ns at CL=50 pF."
},
{
"number": "16",
"name": "Q6",
"type": "output",
"description": "Registered Q output of flip-flop 6; assumes state of D6 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL ≤15 ns at CL=50 pF."
},
{
"number": "17",
"name": "D6",
"type": "input",
"description": "Data input for flip-flop 6; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input leakage ≤±1 µA at VCC=5.5 V."
},
{
"number": "18",
"name": "D5",
"type": "input",
"description": "Data input for flip-flop 5; VIH ≥2 V, VIL ≤0.8 V (HCT); set-up time ≥12 ns, hold time ≥3 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
},
{
"number": "19",
"name": "Q5",
"type": "output",
"description": "Registered Q output of flip-flop 5; assumes state of D5 on rising CP edge when E is Low; VOH ≥3.98 V / VOL ≤0.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Positive supply voltage for HCT type; operating range 4.5 V to 5.5 V; quiescent ICC ≤8 µA typ / 80 µA max at 25 °C; absolute maximum −0.5 V to 7 V."
}
],
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"primary_model": "claude-haiku-4-5-20251001",
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"at": "2026-09-24T23:24:36"
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"Package": "SOIC-20-300mil",
"Category": "Logic",
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