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Ray Publish 0.1.0 74bfca4 11d ago
{
  "slug": "cd74hct377m96",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd74hct377m96",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd74hct377m96.kicad_sym",
    "cd74hct377m96.kicad_mod",
    "cd74hct377m96.glb",
    "cd74hct377m96.step",
    "cd74hct377m96.lbr",
    "docs/hero.png",
    "docs/cd74hct377m96-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "component": {
    "mpn": "CD74HCT377M96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-20-300mil",
    "pin_count": 20,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct377",
    "parts": {
      "symbol": "cd74hct377m96.kicad_sym",
      "footprint": "cd74hct377m96.kicad_mod",
      "model_3d": "cd74hct377m96-etched.glb",
      "model_3d_plain": "cd74hct377m96.glb",
      "model_3d_step": "cd74hct377m96-etched.step",
      "model_3d_step_plain": "cd74hct377m96.step",
      "lbr": "cd74hct377m96.lbr"
    },
    "distributor_links": {
      "lcsc": "C2677836",
      "digikey": "296-38703-2-ND",
      "mouser": "595-CD74HCT377M96"
    },
    "distributor_check": {
      "checked_at": "2026-09-24T23:24:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-38703-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-CD74HCT377M96",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "E",
        "type": "input",
        "description": "Active-low data enable input common to all eight flip-flops; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns before rising CP edge at VCC=4.5 V; presents 1.5 HCT unit loads (\u2264360 \u00b5A each at 25 \u00b0C)."
      },
      {
        "number": "2",
        "name": "Q0",
        "type": "output",
        "description": "Registered Q output of flip-flop 0; assumes state of D0 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; propagation delay tPHL/tPLH \u226438 ns at CL=50 pF, VCC=4.5 V."
      },
      {
        "number": "3",
        "name": "D0",
        "type": "input",
        "description": "Data input for flip-flop 0; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."
      },
      {
        "number": "4",
        "name": "D1",
        "type": "input",
        "description": "Data input for flip-flop 1; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; presents 0.25 HCT unit loads."
      },
      {
        "number": "5",
        "name": "Q1",
        "type": "output",
        "description": "Registered Q output of flip-flop 1; assumes state of D1 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
      },
      {
        "number": "6",
        "name": "Q2",
        "type": "output",
        "description": "Registered Q output of flip-flop 2; assumes state of D2 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL \u226438 ns at CL=50 pF."
      },
      {
        "number": "7",
        "name": "D2",
        "type": "input",
        "description": "Data input for flip-flop 2; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input leakage \u2264\u00b11 \u00b5A at VCC=5.5 V."
      },
      {
        "number": "8",
        "name": "D3",
        "type": "input",
        "description": "Data input for flip-flop 3; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
      },
      {
        "number": "9",
        "name": "Q3",
        "type": "output",
        "description": "Registered Q output of flip-flop 3; assumes state of D3 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL \u226415 ns at CL=50 pF."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground supply reference for all internal logic; DC GND current ICC/IGND must not exceed \u00b150 mA absolute maximum."
      },
      {
        "number": "11",
        "name": "CP",
        "type": "input",
        "description": "Buffered clock input common to all eight flip-flops; flip-flops load on rising edge when E is Low; maximum clock frequency 25 MHz at VCC=4.5 V; clock pulse width tW \u226520 ns at VCC=4.5 V; presents 0.5 HCT unit loads."
      },
      {
        "number": "12",
        "name": "Q7",
        "type": "output",
        "description": "Registered Q output of flip-flop 7; assumes state of D7 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
      },
      {
        "number": "13",
        "name": "D7",
        "type": "input",
        "description": "Data input for flip-flop 7; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input leakage \u2264\u00b11 \u00b5A at VCC=5.5 V."
      },
      {
        "number": "14",
        "name": "D4",
        "type": "input",
        "description": "Data input for flip-flop 4; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
      },
      {
        "number": "15",
        "name": "Q4",
        "type": "output",
        "description": "Registered Q output of flip-flop 4; assumes state of D4 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; tPLH/tPHL \u226438 ns at CL=50 pF."
      },
      {
        "number": "16",
        "name": "Q6",
        "type": "output",
        "description": "Registered Q output of flip-flop 6; assumes state of D6 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; output transition time tTLH/tTHL \u226415 ns at CL=50 pF."
      },
      {
        "number": "17",
        "name": "D6",
        "type": "input",
        "description": "Data input for flip-flop 6; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input leakage \u2264\u00b11 \u00b5A at VCC=5.5 V."
      },
      {
        "number": "18",
        "name": "D5",
        "type": "input",
        "description": "Data input for flip-flop 5; VIH \u22652 V, VIL \u22640.8 V (HCT); set-up time \u226512 ns, hold time \u22653 ns relative to rising CP edge at VCC=4.5 V; input capacitance 10 pF typ."
      },
      {
        "number": "19",
        "name": "Q5",
        "type": "output",
        "description": "Registered Q output of flip-flop 5; assumes state of D5 on rising CP edge when E is Low; VOH \u22653.98 V / VOL \u22640.26 V at VCC=4.5 V with 4 mA TTL load; fanout 10 LSTTL loads over temperature."
      },
      {
        "number": "20",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage for HCT type; operating range 4.5 V to 5.5 V; quiescent ICC \u22648 \u00b5A typ / 80 \u00b5A max at 25 \u00b0C; absolute maximum \u22120.5 V to 7 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-4-6",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 20,
        "cost_usd": 0.3518,
        "at": "2026-09-24T23:24:36"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hct377",
        "pages": 20,
        "sha256": "e31605c6c3b60b6d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    }
  }
}