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CD74HCT373M96
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# CD74HCT373M96++**Texas Instruments** · Latches · SOIC-20-300mil++CD74HCT373M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered output-enable input that places the eight outputs in a normal logic state (low) or the high-impedance state (high), without affecting the latches' internal operation. |+| 2 | 1Q | tri_state | Channel 1 latch output that follows 1D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 3 | 1D | input | Channel 1 data input to the transparent D-type latch. |+| 4 | 2D | input | Channel 2 data input to the transparent D-type latch. |+| 5 | 2Q | tri_state | Channel 2 latch output that follows 2D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 6 | 3Q | tri_state | Channel 3 latch output that follows 3D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 7 | 3D | input | Channel 3 data input to the transparent D-type latch. |+| 8 | 4D | input | Channel 4 data input to the transparent D-type latch. |+| 9 | 4Q | tri_state | Channel 4 latch output that follows 4D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 10 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±50 mA. |+| 11 | LE | input | Latch-enable input; Q outputs follow D inputs when high and are latched at the D logic levels when low. |+| 12 | 5Q | tri_state | Channel 5 latch output that follows 5D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 13 | 5D | input | Channel 5 data input to the transparent D-type latch. |+| 14 | 6D | input | Channel 6 data input to the transparent D-type latch. |+| 15 | 6Q | tri_state | Channel 6 latch output that follows 6D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 16 | 7Q | tri_state | Channel 7 latch output that follows 7D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 17 | 7D | input | Channel 7 data input to the transparent D-type latch. |+| 18 | 8D | input | Channel 8 data input to the transparent D-type latch. |+| 19 | 8Q | tri_state | Channel 8 latch output that follows 8D when LE is high, is latched when LE is low, and is high-impedance when OE is high. |+| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended, with a 0.1-μF bypass capacitor placed close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CD74HCT373M96`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `cd74hct373m96-etched.step` / `cd74hct373m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct373m96.step` / `cd74hct373m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct373) (20 pp, sha256 `fe27465b065a13ce`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hct373m96-datasheet.pdf)
page.jsonadded+230@@ -0,0 +1,230 @@+{+ "slug": "cd74hct373m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hct373m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hct373m96.kicad_sym",+ "cd74hct373m96.kicad_mod",+ "cd74hct373m96.glb",+ "cd74hct373m96.step",+ "cd74hct373m96.lbr",+ "docs/hero.png",+ "docs/cd74hct373m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74HCT373M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct373",+ "parts": {+ "symbol": "cd74hct373m96.kicad_sym",+ "footprint": "cd74hct373m96.kicad_mod",+ "model_3d": "cd74hct373m96-etched.glb",+ "model_3d_plain": "cd74hct373m96.glb",+ "model_3d_step": "cd74hct373m96-etched.step",+ "model_3d_step_plain": "cd74hct373m96.step",+ "lbr": "cd74hct373m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2675306",+ "digikey": "296-31614-2-ND",+ "mouser": "595-CD74HCT373M96"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T04:01:28Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-31614-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HCT373M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Buffered output-enable input that places the eight outputs in a normal logic state (low) or the high-impedance state (high), without affecting the latches' internal operation."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "tri_state",+ "description": "Channel 1 latch output that follows 1D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Channel 1 data input to the transparent D-type latch."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Channel 2 data input to the transparent D-type latch."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "tri_state",+ "description": "Channel 2 latch output that follows 2D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "tri_state",+ "description": "Channel 3 latch output that follows 3D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Channel 3 data input to the transparent D-type latch."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Channel 4 data input to the transparent D-type latch."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "tri_state",+ "description": "Channel 4 latch output that follows 4D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; continuous current through VCC or GND is limited to ±50 mA."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch-enable input; Q outputs follow D inputs when high and are latched at the D logic levels when low."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "tri_state",+ "description": "Channel 5 latch output that follows 5D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Channel 5 data input to the transparent D-type latch."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Channel 6 data input to the transparent D-type latch."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "tri_state",+ "description": "Channel 6 latch output that follows 6D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "tri_state",+ "description": "Channel 7 latch output that follows 7D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Channel 7 data input to the transparent D-type latch."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Channel 8 data input to the transparent D-type latch."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "tri_state",+ "description": "Channel 8 latch output that follows 8D when LE is high, is latched when LE is low, and is high-impedance when OE is high."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V recommended, with a 0.1-μF bypass capacitor placed close to the pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin configuration diagram on page 3 is in ASCII format and cannot be reliably parsed; pinout has"+ ],+ "pages_sent": 20,+ "cost_usd": 0.1686,+ "at": "2026-10-01T04:01:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct373",+ "pages": 20,+ "sha256": "fe27465b065a13ce",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}