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Contents

README

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CD74HCT373M96

Texas Instruments · Latches · SOIC-20-300mil

CD74HCT373M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input that places the eight outputs in a normal logic state (low) or the high-impedance state (high), without affecting the latches' internal operation.
2 1Q tri_state Channel 1 latch output that follows 1D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
3 1D input Channel 1 data input to the transparent D-type latch.
4 2D input Channel 2 data input to the transparent D-type latch.
5 2Q tri_state Channel 2 latch output that follows 2D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
6 3Q tri_state Channel 3 latch output that follows 3D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
7 3D input Channel 3 data input to the transparent D-type latch.
8 4D input Channel 4 data input to the transparent D-type latch.
9 4Q tri_state Channel 4 latch output that follows 4D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
10 GND power_in Ground; continuous current through VCC or GND is limited to ±50 mA.
11 LE input Latch-enable input; Q outputs follow D inputs when high and are latched at the D logic levels when low.
12 5Q tri_state Channel 5 latch output that follows 5D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
13 5D input Channel 5 data input to the transparent D-type latch.
14 6D input Channel 6 data input to the transparent D-type latch.
15 6Q tri_state Channel 6 latch output that follows 6D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
16 7Q tri_state Channel 7 latch output that follows 7D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
17 7D input Channel 7 data input to the transparent D-type latch.
18 8D input Channel 8 data input to the transparent D-type latch.
19 8Q tri_state Channel 8 latch output that follows 8D when LE is high, is latched when LE is low, and is high-impedance when OE is high.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended, with a 0.1-μF bypass capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74HCT373M96
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74hct373m96-etched.step / cd74hct373m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct373m96.step / cd74hct373m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 fe27465b065a13ce, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF