component
CD74HCT299M96
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "CD74HCT299M96",
"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
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"digikey": "296-31610-2-ND",
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"pins": [
{
"number": "1",
"name": "S0",
"type": "input",
"description": "Mode select input S0, sampled on the low-to-high clock transition and must be stable one setup time before the clock edge (S0 and S1 both high loads the register)."
},
{
"number": "2",
"name": "OE1",
"type": "input",
"description": "Output enable 1; when either OE1 or OE2 is high the I/O terminals are forced to the off (high-impedance) state."
},
{
"number": "3",
"name": "OE2",
"type": "input",
"description": "Output enable 2; when either OE1 or OE2 is high the I/O terminals are forced to the off (high-impedance) state."
},
{
"number": "4",
"name": "I/O6",
"type": "bidirectional",
"description": "Three-state parallel data input/output 6 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "5",
"name": "I/O4",
"type": "bidirectional",
"description": "Three-state parallel data input/output 4 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "6",
"name": "I/O2",
"type": "bidirectional",
"description": "Three-state parallel data input/output 2 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "7",
"name": "I/O0",
"type": "bidirectional",
"description": "Three-state parallel data input/output 0 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "8",
"name": "Q0",
"type": "output",
"description": "Standard serial output (10 LSTTL loads) for the first register stage, tied to DS7 of the preceding register when cascading."
},
{
"number": "9",
"name": "MR",
"type": "input",
"description": "Asynchronous active-low master reset that clears the register regardless of all other inputs."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Ground (0 V) supply pin."
},
{
"number": "11",
"name": "DS0",
"type": "input",
"description": "Serial data input for shift right, sampled on the low-to-high clock transition; tied to Q7 of the preceding register when cascading."
},
{
"number": "12",
"name": "CP",
"type": "input",
"description": "Clock pulse input; mode select, serial data and parallel data respond only to its low-to-high transition."
},
{
"number": "13",
"name": "I/O1",
"type": "bidirectional",
"description": "Three-state parallel data input/output 1 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "14",
"name": "I/O3",
"type": "bidirectional",
"description": "Three-state parallel data input/output 3 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "15",
"name": "I/O5",
"type": "bidirectional",
"description": "Three-state parallel data input/output 5 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "16",
"name": "I/O7",
"type": "bidirectional",
"description": "Three-state parallel data input/output 7 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high."
},
{
"number": "17",
"name": "Q7",
"type": "output",
"description": "Standard serial output (10 LSTTL loads) for the last register stage, tied to DS0 of the following register when cascading."
},
{
"number": "18",
"name": "DS7",
"type": "input",
"description": "Serial data input for shift left, sampled on the low-to-high clock transition; tied to Q0 of the following register when cascading."
},
{
"number": "19",
"name": "S1",
"type": "input",
"description": "Mode select input S1, sampled on the low-to-high clock transition and must be stable one setup time before the clock edge (S0 and S1 both high loads the register)."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Positive supply voltage, 4.5V to 5.5V for HCT types."
}
],
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"primary_model": "claude-haiku-5-5",
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"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pinout diagram in the text extraction is scrambled (labels and numbers are separated), so pin nu; The datasheet covers SOIC (M/M96 suffix, 20-Ld SOIC) and PDIP; the pinout is shared across the packa; Pin types for I/O0-I/O7 are set to bidirectional because the datasheet describes each as a three-sta"
],
"pages_sent": 20,
"cost_usd": 0.0973,
"at": "2026-10-11T07:27:22"
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"pages": 20,
"sha256": "d3c541dfd0acb057",
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