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CD74HCT299M96

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT299M96

Texas Instruments · Latches · SOIC-20-300mil

CD74HCT299M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0 input Mode select input S0, sampled on the low-to-high clock transition and must be stable one setup time before the clock edge (S0 and S1 both high loads the register).
2 OE1 input Output enable 1; when either OE1 or OE2 is high the I/O terminals are forced to the off (high-impedance) state.
3 OE2 input Output enable 2; when either OE1 or OE2 is high the I/O terminals are forced to the off (high-impedance) state.
4 I/O6 bidirectional Three-state parallel data input/output 6 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
5 I/O4 bidirectional Three-state parallel data input/output 4 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
6 I/O2 bidirectional Three-state parallel data input/output 2 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
7 I/O0 bidirectional Three-state parallel data input/output 0 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
8 Q0 output Standard serial output (10 LSTTL loads) for the first register stage, tied to DS7 of the preceding register when cascading.
9 MR input Asynchronous active-low master reset that clears the register regardless of all other inputs.
10 GND power_in Ground (0 V) supply pin.
11 DS0 input Serial data input for shift right, sampled on the low-to-high clock transition; tied to Q7 of the preceding register when cascading.
12 CP input Clock pulse input; mode select, serial data and parallel data respond only to its low-to-high transition.
13 I/O1 bidirectional Three-state parallel data input/output 1 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
14 I/O3 bidirectional Three-state parallel data input/output 3 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
15 I/O5 bidirectional Three-state parallel data input/output 5 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
16 I/O7 bidirectional Three-state parallel data input/output 7 with bus drive capability (15 LSTTL loads), loaded on the clock rising edge when S0 and S1 are high.
17 Q7 output Standard serial output (10 LSTTL loads) for the last register stage, tied to DS0 of the following register when cascading.
18 DS7 input Serial data input for shift left, sampled on the low-to-high clock transition; tied to Q0 of the following register when cascading.
19 S1 input Mode select input S1, sampled on the low-to-high clock transition and must be stable one setup time before the clock edge (S0 and S1 both high loads the register).
20 VCC power_in Positive supply voltage, 4.5V to 5.5V for HCT types.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74HCT299M96
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74hct299m96-etched.step / cd74hct299m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct299m96.step / cd74hct299m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 d3c541dfd0acb057, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF