component
CD74HCT259M96
Public Made by Adomby adom
Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HCT259M96
Texas Instruments · Latches · SOIC-16
CD74HCT259M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S0 | input | Address select input bit 0 (LSB) selecting which of the eight latches is addressed. |
| 2 | S1 | input | Address select input bit 1 selecting which of the eight latches is addressed. |
| 3 | S2 | input | Address select input bit 2 (MSB) selecting which of the eight latches is addressed. |
| 4 | Q0 | output | Latch 0 buffered output, active high. |
| 5 | Q1 | output | Latch 1 buffered output, active high. |
| 6 | Q2 | output | Latch 2 buffered output, active high. |
| 7 | Q3 | output | Latch 3 buffered output, active high. |
| 8 | GND | power_in | Ground reference for the supply. |
| 9 | Q4 | output | Latch 4 buffered output, active high. |
| 10 | Q5 | output | Latch 5 buffered output, active high. |
| 11 | Q6 | output | Latch 6 buffered output, active high. |
| 12 | Q7 | output | Latch 7 buffered output, active high. |
| 13 | D | input | Data input written into the addressed latch. |
| 14 | G | input | Active-low enable input; low allows the addressed latch to follow D, high holds the latches in memory mode. |
| 15 | CLR | input | Active-low clear input; with G high all outputs are cleared low, with G low it selects 1-of-8 decoder mode. |
| 16 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1 µF bypass capacitor recommended. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage (HCT) | VIH | 2 | V | VCC = 4.5 to 5.5 V, 25°C | 5 | ||
| Low-level input voltage (HCT) | VIL | 0.8 | V | VCC = 4.5 to 5.5 V, 25°C | 5 | ||
| High-level output voltage (HCT) | VOH | 4.4 | V | VOH = -20 µA, VCC = 4.5 V, 25°C | 5 | ||
| High-level output voltage (HCT) | VOH | 3.98 | V | VOH = -4 mA, VCC = 4.5 V, 25°C | 5 | ||
| High-level output voltage (HCT) | VOH | 3.84 | V | VOH = -4 mA, VCC = 4.5 V, -40°C to 85°C | 5 | ||
| High-level output voltage (HCT) | VOH | 3.7 | V | VOH = -4 mA, VCC = 4.5 V, -55°C to 125°C | 5 | ||
| Low-level output voltage (HCT) | VOL | 0.1 | V | VOL = 20 µA, VCC = 4.5 V, 25°C | 5 | ||
| Low-level output voltage (HCT) | VOL | 0.26 | V | VOL = 4 mA, VCC = 4.5 V, 25°C | 5 | ||
| Low-level output voltage (HCT) | VOL | 0.33 | V | VOL = 4 mA, VCC = 4.5 V, -40°C to 85°C | 5 | ||
| Low-level output voltage (HCT) | VOL | 0.4 | V | VOL = 4 mA, VCC = 4.5 V, -55°C to 125°C | 5 | ||
| Input leakage current (HCT) | II | -1 | 1 | µA | VI = VCC or GND, VCC = 5.5 V, -40°C to 85°C | 5 | |
| Supply current (HCT) | ICC | 80 | µA | VI = VCC or GND, VCC = 5.5 V, -40°C to 85°C | 5 | ||
| Supply current (HCT) | ICC | 160 | µA | VI = VCC or GND, VCC = 5.5 V, -55°C to 125°C | 5 | ||
| Pulse width G (HCT) | tWL | 18 | ns | VCC = 4.5 V, 25°C | 6 | ||
| Pulse width G (HCT) | tWL | 23 | ns | VCC = 4.5 V, -40°C to 85°C | 6 | ||
| Pulse width G (HCT) | tWL | 27 | ns | VCC = 4.5 V, -55°C to 125°C | 6 | ||
| Pulse width CLR (HCT) | tWL | 18 | ns | VCC = 4.5 V, 25°C | 6 | ||
| Pulse width CLR (HCT) | tWL | 23 | ns | VCC = 4.5 V, -40°C to 85°C | 6 | ||
| Pulse width CLR (HCT) | tWL | 27 | ns | VCC = 4.5 V, -55°C to 125°C | 6 | ||
| Setup time D to G, S to G (HCT) | tSU | 17 | ns | VCC = 4.5 V, 25°C | 6 | ||
| Setup time D to G, S to G (HCT) | tSU | 21 | ns | VCC = 4.5 V, -40°C to 85°C | 6 | ||
| Setup time D to G, S to G (HCT) | tSU | 26 | ns | VCC = 4.5 V, -55°C to 125°C | 6 | ||
| Hold time D to G, S to G (HCT) | tH | 0 | pF | VCC = 4.5 V, 25°C | 6 | ||
| Propagation delay D to Q (HCT) | tpd | 39 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 | ||
| Propagation delay D to Q (HCT) | tpd | 49 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 | ||
| Propagation delay D to Q (HCT) | tpd | 59 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 | ||
| Propagation delay G to Q (HCT) | tpd | 38 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 | ||
| Propagation delay G to Q (HCT) | tpd | 48 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 | ||
| Propagation delay G to Q (HCT) | tpd | 57 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 | ||
| Propagation delay S to Q (HCT) | tpd | 41 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 | ||
| Propagation delay S to Q (HCT) | tpd | 51 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 | ||
| Propagation delay S to Q (HCT) | tpd | 61 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 | ||
| Propagation delay CLR to Q (HCT) | tpd | 39 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 | ||
| Propagation delay CLR to Q (HCT) | tpd | 49 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 | ||
| Propagation delay CLR to Q (HCT) | tpd | 59 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 | ||
| Supply voltage range (HCT types) | VCC | 4.5 | 5.5 | V | HCT types | 4 | |
| Input rise and fall time | tt | 500 | ns | VCC = 4.5 V | 4 | ||
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp diode current | IIK | -20 | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp diode current | IOK | -20 | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Drain current, per output | IO | -25 | 25 | mA | For -0.5 V < VO < VCC + 0.5 V | 4 | |
| Output source or sink current per output pin | IO | -25 | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature (soldering 10 s) | 300 | °C | 10 s, SOIC lead tips only | 4 | |||
| Junction-to-ambient thermal resistance (D, SOIC) | RθJA | 73 | °C/W | D (SOIC) package, 16 pins | 4 |
CAD (KiCad official)
- Symbol:
CD74HCT259M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hct259m96-etched.step/cd74hct259m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct259m96.step/cd74hct259m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
b5b0452744156ee1, retrieved 2026-10-18, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HCT259M96
**Texas Instruments** · Latches · SOIC-16
CD74HCT259M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S0 | input | Address select input bit 0 (LSB) selecting which of the eight latches is addressed. |
| 2 | S1 | input | Address select input bit 1 selecting which of the eight latches is addressed. |
| 3 | S2 | input | Address select input bit 2 (MSB) selecting which of the eight latches is addressed. |
| 4 | Q0 | output | Latch 0 buffered output, active high. |
| 5 | Q1 | output | Latch 1 buffered output, active high. |
| 6 | Q2 | output | Latch 2 buffered output, active high. |
| 7 | Q3 | output | Latch 3 buffered output, active high. |
| 8 | GND | power_in | Ground reference for the supply. |
| 9 | Q4 | output | Latch 4 buffered output, active high. |
| 10 | Q5 | output | Latch 5 buffered output, active high. |
| 11 | Q6 | output | Latch 6 buffered output, active high. |
| 12 | Q7 | output | Latch 7 buffered output, active high. |
| 13 | D | input | Data input written into the addressed latch. |
| 14 | G | input | Active-low enable input; low allows the addressed latch to follow D, high holds the latches in memory mode. |
| 15 | CLR | input | Active-low clear input; with G high all outputs are cleared low, with G low it selects 1-of-8 decoder mode. |
| 16 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1 µF bypass capacitor recommended. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage (HCT) | VIH | 2 | | | V | VCC = 4.5 to 5.5 V, 25°C | 5 |
| Low-level input voltage (HCT) | VIL | | | 0.8 | V | VCC = 4.5 to 5.5 V, 25°C | 5 |
| High-level output voltage (HCT) | VOH | 4.4 | | | V | VOH = -20 µA, VCC = 4.5 V, 25°C | 5 |
| High-level output voltage (HCT) | VOH | 3.98 | | | V | VOH = -4 mA, VCC = 4.5 V, 25°C | 5 |
| High-level output voltage (HCT) | VOH | 3.84 | | | V | VOH = -4 mA, VCC = 4.5 V, -40°C to 85°C | 5 |
| High-level output voltage (HCT) | VOH | 3.7 | | | V | VOH = -4 mA, VCC = 4.5 V, -55°C to 125°C | 5 |
| Low-level output voltage (HCT) | VOL | | | 0.1 | V | VOL = 20 µA, VCC = 4.5 V, 25°C | 5 |
| Low-level output voltage (HCT) | VOL | | | 0.26 | V | VOL = 4 mA, VCC = 4.5 V, 25°C | 5 |
| Low-level output voltage (HCT) | VOL | | | 0.33 | V | VOL = 4 mA, VCC = 4.5 V, -40°C to 85°C | 5 |
| Low-level output voltage (HCT) | VOL | | | 0.4 | V | VOL = 4 mA, VCC = 4.5 V, -55°C to 125°C | 5 |
| Input leakage current (HCT) | II | -1 | | 1 | µA | VI = VCC or GND, VCC = 5.5 V, -40°C to 85°C | 5 |
| Supply current (HCT) | ICC | | | 80 | µA | VI = VCC or GND, VCC = 5.5 V, -40°C to 85°C | 5 |
| Supply current (HCT) | ICC | | | 160 | µA | VI = VCC or GND, VCC = 5.5 V, -55°C to 125°C | 5 |
| Pulse width G (HCT) | tWL | 18 | | | ns | VCC = 4.5 V, 25°C | 6 |
| Pulse width G (HCT) | tWL | 23 | | | ns | VCC = 4.5 V, -40°C to 85°C | 6 |
| Pulse width G (HCT) | tWL | 27 | | | ns | VCC = 4.5 V, -55°C to 125°C | 6 |
| Pulse width CLR (HCT) | tWL | 18 | | | ns | VCC = 4.5 V, 25°C | 6 |
| Pulse width CLR (HCT) | tWL | 23 | | | ns | VCC = 4.5 V, -40°C to 85°C | 6 |
| Pulse width CLR (HCT) | tWL | 27 | | | ns | VCC = 4.5 V, -55°C to 125°C | 6 |
| Setup time D to G, S to G (HCT) | tSU | 17 | | | ns | VCC = 4.5 V, 25°C | 6 |
| Setup time D to G, S to G (HCT) | tSU | 21 | | | ns | VCC = 4.5 V, -40°C to 85°C | 6 |
| Setup time D to G, S to G (HCT) | tSU | 26 | | | ns | VCC = 4.5 V, -55°C to 125°C | 6 |
| Hold time D to G, S to G (HCT) | tH | 0 | | | pF | VCC = 4.5 V, 25°C | 6 |
| Propagation delay D to Q (HCT) | tpd | | | 39 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 |
| Propagation delay D to Q (HCT) | tpd | | | 49 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 |
| Propagation delay D to Q (HCT) | tpd | | | 59 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 |
| Propagation delay G to Q (HCT) | tpd | | | 38 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 |
| Propagation delay G to Q (HCT) | tpd | | | 48 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 |
| Propagation delay G to Q (HCT) | tpd | | | 57 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 |
| Propagation delay S to Q (HCT) | tpd | | | 41 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 |
| Propagation delay S to Q (HCT) | tpd | | | 51 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 |
| Propagation delay S to Q (HCT) | tpd | | | 61 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 |
| Propagation delay CLR to Q (HCT) | tpd | | | 39 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, 25°C | 7 |
| Propagation delay CLR to Q (HCT) | tpd | | | 49 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -40°C to 85°C | 7 |
| Propagation delay CLR to Q (HCT) | tpd | | | 59 | ns | CL = 50 pF, input tt = 6 ns, VCC = 4.5 V, -55°C to 125°C | 7 |
| Supply voltage range (HCT types) | VCC | 4.5 | | 5.5 | V | HCT types | 4 |
| Input rise and fall time | tt | | | 500 | ns | VCC = 4.5 V | 4 |
| Temperature range | TA | -55 | | 125 | °C | | 4 |
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp diode current | IIK | -20 | | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp diode current | IOK | -20 | | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Drain current, per output | IO | -25 | | 25 | mA | For -0.5 V < VO < VCC + 0.5 V | 4 |
| Output source or sink current per output pin | IO | -25 | | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 |
| Continuous current through VCC or GND | | -50 | | 50 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Lead temperature (soldering 10 s) | | | | 300 | °C | 10 s, SOIC lead tips only | 4 |
| Junction-to-ambient thermal resistance (D, SOIC) | RθJA | | 73 | | °C/W | D (SOIC) package, 16 pins | 4 |
## CAD (KiCad official)
- Symbol: `CD74HCT259M96`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `cd74hct259m96-etched.step` / `cd74hct259m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct259m96.step` / `cd74hct259m96.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hct259m96.pdf) (23 pp, sha256 `b5b0452744156ee1`, retrieved 2026-10-18, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hct259m96-datasheet.pdf)