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CD74HCT21M

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Texas Instruments Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT21M

Texas Instruments · Gates · SOIC-14

CD74HCT21M from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 input A of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
2 1B input Channel 1 input B of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
3 NC unconnected Not internally connected; the datasheet lists this pin as NC and it may be left unconnected.
4 1C input Channel 1 input C of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
5 1D input Channel 1 input D of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
6 1Y output Channel 1 output Y of the 4-input AND gate, a balanced CMOS push-pull output; it drives HIGH only when all four inputs are HIGH.
7 GND power_in Ground reference for the device; the absolute maximum continuous current through VCC or GND is ±50 mA.
8 2Y output Channel 2 output Y of the 4-input AND gate, a balanced CMOS push-pull output; it drives HIGH only when all four inputs are HIGH.
9 2A input Channel 2 input A of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
10 2B input Channel 2 input B of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
11 NC unconnected Not internally connected; the datasheet lists this pin as NC and it may be left unconnected.
12 2C input Channel 2 input C of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
13 2D input Channel 2 input D of the 4-input AND gate (Y = A·B·C·D); inputs are LSTTL/CMOS compatible with VIL(max) = 0.8 V and VIH(min) = 2 V at 4.5 V to 5.5 V VCC.
14 VCC power_in Positive supply, 4.5 V to 5.5 V recommended operating range, with absolute maximum rating of 7 V; a 0.1 µF bypass capacitor is recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -25 25 mA VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Lead temperature (soldering 10s) 300 °C 10 s, SOIC - Lead Tips Only 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Input transition rise and fall time tt 500 ns VCC = 4.5 V 4
Input transition rise and fall time tt 400 ns VCC = 5.5 V 4
Operating free-air temperature TA -55 125 °C 4
High-level output voltage (TA 25°C) VOH 4.4 V VI = VIH, IOH = -20 µA, VCC 4.5 V 5
High-level output voltage (TA -40°C to 85°C) VOH 4.4 V VI = VIH, IOH = -20 µA, VCC 4.5 V 5
High-level output voltage (TA -55°C to 125°C) VOH 4.4 V VI = VIH, IOH = -20 µA, VCC 4.5 V 5
High-level output voltage (TA 25°C) VOH 3.98 V VI = VIH, IOH = -4 mA, VCC 4.5 V 5
High-level output voltage (TA -40°C to 85°C) VOH 3.84 V VI = VIH, IOH = -4 mA, VCC 4.5 V 5
High-level output voltage (TA -55°C to 125°C) VOH 3.7 V VI = VIH, IOH = -4 mA, VCC 4.5 V 5
Low-level output voltage (TA 25°C) VOL 0.1 V VI = VIL, IOL = 20 µA, VCC 4.5 V 5
Low-level output voltage (TA -40°C to 85°C) VOL 0.1 V VI = VIL, IOL = 20 µA, VCC 4.5 V 5
Low-level output voltage (TA -55°C to 125°C) VOL 0.1 V VI = VIL, IOL = 20 µA, VCC 4.5 V 5
Low-level output voltage (TA 25°C) VOL 0.26 V VI = VIL, IOL = 4 mA, VCC 4.5 V 5
Low-level output voltage (TA -40°C to 85°C) VOL 0.33 V VI = VIL, IOL = 4 mA, VCC 4.5 V 5
Low-level output voltage (TA -55°C to 125°C) VOL 0.4 V VI = VIL, IOL = 4 mA, VCC 4.5 V 5
Input leakage current (TA 25°C) II -0.1 0.1 µA VI = VCC and GND, IO = 0, VCC 5.5 V 5
Input leakage current (TA -40°C to 85°C) II -1 1 µA VI = VCC and GND, IO = 0, VCC 5.5 V 5
Input leakage current (TA -55°C to 125°C) II -1 1 µA VI = VCC and GND, IO = 0, VCC 5.5 V 5
Supply current (TA 25°C) ICC 2 µA VI = VCC or GND, IO = 0, VCC 5.5 V 5
Supply current (TA -40°C to 85°C) ICC 20 µA VI = VCC or GND, IO = 0, VCC 5.5 V 5
Supply current (TA -55°C to 125°C) ICC 40 µA VI = VCC or GND, IO = 0, VCC 5.5 V 5
Additional quiescent device current per input pin (TA 25°C) ΔICC 100 360 µA VI = VCC, 2.1, VCC 4.5 V to 5.5 V 5
Additional quiescent device current per input pin (TA -40°C to 85°C) ΔICC 450 µA VI = VCC, 2.1, VCC 4.5 V to 5.5 V 5
Additional quiescent device current per input pin (TA -55°C to 125°C) ΔICC 490 µA VI = VCC, 2.1, VCC 4.5 V to 5.5 V 5
Propagation delay A, B, C or D to Y (TA 25°C) tpd 27 ns CL = 50 pF, VCC 4.5 V 5
Propagation delay A, B, C or D to Y (TA -40°C to 85°C) tpd 34 ns CL = 50 pF, VCC 4.5 V 5
Propagation delay A, B, C or D to Y (TA -55°C to 125°C) tpd 41 ns CL = 50 pF, VCC 4.5 V 5
Transition time (TA 25°C) tt 15 ns CL = 50 pF, VCC 4.5 V 5
Transition time (TA -40°C to 85°C) tt 19 ns CL = 50 pF, VCC 4.5 V 5
Transition time (TA -55°C to 125°C) tt 22 ns CL = 50 pF, VCC 4.5 V 5
Junction-to-ambient thermal resistance (D SOIC 14-pin) RθJA 102.3 °C/W 4
Junction-to-case (top) thermal resistance (D SOIC 14-pin) RθJC(top) 58.7 °C/W 4
Junction-to-board thermal resistance (D SOIC 14-pin) RθJB 58.2 °C/W 4
Junction-to-top characterization parameter (D SOIC 14-pin) ΨJT 19.9 °C/W 5
Junction-to-board characterization parameter (D SOIC 14-pin) ΨJB 57.8 °C/W 5

CAD (KiCad official)

  • Symbol: CD74HCT21M
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hct21m-etched.step / cd74hct21m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct21m.step / cd74hct21m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 11fe0afbe009c65b, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF