CD74HCT175M96

{
  "slug": "cd74hct175m96",
  "version": "0.1.1",
  "type": "component",
  "description": "Texas Instruments Flip Flops, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "cd74hct175m96",
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    "extractor-text"
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  "dependencies": {},
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    "cd74hct175m96.step",
    "cd74hct175m96.lbr",
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    "docs/cd74hct175m96-datasheet.pdf",
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    "viewers/footprint.html",
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    "cd74hct175m96-hero.overlay.json",
    "cd74hct175m96-etched.glb"
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  "component": {
    "mpn": "CD74HCT175M96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd74hct175m96.pdf",
    "parts": {
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      "footprint": "cd74hct175m96.kicad_mod",
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      "model_3d_plain": "cd74hct175m96-etched.glb",
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      "model_3d_step_plain": "cd74hct175m96.step",
      "lbr": "cd74hct175m96.lbr"
    },
    "distributor_links": {
      "lcsc": "C8137",
      "digikey": "296-12837-2-ND",
      "mouser": "595-CD74HCT175M96"
    },
    "distributor_check": {
      "checked_at": "2026-11-05T23:45:48Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-12837-2-ND",
        "status": "found"
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      "mouser": {
        "pn": "595-CD74HCT175M96",
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    },
    "pins": [
      {
        "number": "1",
        "name": "MR",
        "type": "input",
        "description": "Active-low common asynchronous reset that sets all four Q outputs to logic 0 and all Q-bar outputs to logic 1 independent of the clock; MR pulse width tw is 20 ns min at 4.5 V."
      },
      {
        "number": "2",
        "name": "Q0",
        "type": "output",
        "description": "True output of flip-flop 0, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature."
      },
      {
        "number": "3",
        "name": "Q0_bar",
        "type": "output",
        "description": "Complementary output of flip-flop 0, which is reset to logic 1 by MR."
      },
      {
        "number": "4",
        "name": "D0",
        "type": "input",
        "description": "Data input of flip-flop 0, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V."
      },
      {
        "number": "5",
        "name": "D1",
        "type": "input",
        "description": "Data input of flip-flop 1, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V."
      },
      {
        "number": "6",
        "name": "Q1_bar",
        "type": "output",
        "description": "Complementary output of flip-flop 1, which is reset to logic 1 by MR."
      },
      {
        "number": "7",
        "name": "Q1",
        "type": "output",
        "description": "True output of flip-flop 1, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device; DC input or output voltage range is 0 V to VCC."
      },
      {
        "number": "9",
        "name": "CP",
        "type": "input",
        "description": "Common clock input; data is captured on the positive-going edge, with clock pulse width tw of 20 ns min and fMAX of 25 MHz min at 4.5 V."
      },
      {
        "number": "10",
        "name": "Q2",
        "type": "output",
        "description": "True output of flip-flop 2, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature."
      },
      {
        "number": "11",
        "name": "Q2_bar",
        "type": "output",
        "description": "Complementary output of flip-flop 2, which is reset to logic 1 by MR."
      },
      {
        "number": "12",
        "name": "D2",
        "type": "input",
        "description": "Data input of flip-flop 2, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V."
      },
      {
        "number": "13",
        "name": "D3",
        "type": "input",
        "description": "Data input of flip-flop 3, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V."
      },
      {
        "number": "14",
        "name": "Q3_bar",
        "type": "output",
        "description": "Complementary output of flip-flop 3, which is reset to logic 1 by MR."
      },
      {
        "number": "15",
        "name": "Q3",
        "type": "output",
        "description": "True output of flip-flop 3, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage for HCT types, specified from 4.5 V to 5.5 V (absolute maximum 7 V)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd74hct175m96.pdf",
        "pages": 16,
        "sha256": "577b40c4b30ac148",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
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    ],
    "package_dims": {
      "package_code": "D",
      "E1": {
        "nom_mm": 3.9,
        "range_mm": null
      },
      "E": {
        "nom_mm": 6.0,
        "range_mm": null
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": null
      },
      "source": "TI package designator D (no drawing in the datasheet)",
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        "verdict": "SKIP",
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}