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CD74HCT175M96

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Texas Instruments Flip Flops, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hct175m96factory-2.0.0extractor-text

Verified CD74HCT175M96

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HCT175M96 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 16-page datasheet
  • ✓distributor: lcsc C8137, digikey 296-12837-2-ND, mouser 595-CD74HCT175M96
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rwan640l/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hct175m96.kicad_sym✓ cd74hct175m96.kicad_mod✓ cd74hct175m96.step
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CD74HCT175M96

Texas Instruments · Flip Flops · SOIC-16

CD74HCT175M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ~{MR} input Active-low common asynchronous reset that sets all four Q outputs to logic 0 and all Q-bar outputs to logic 1 independent of the clock; MR pulse width tw is 20 ns min at 4.5 V.
2 Q0 output True output of flip-flop 0, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature.
3 ~{Q0} output Complementary output of flip-flop 0, which is reset to logic 1 by MR.
4 D0 input Data input of flip-flop 0, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V.
5 D1 input Data input of flip-flop 1, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V.
6 ~{Q1} output Complementary output of flip-flop 1, which is reset to logic 1 by MR.
7 Q1 output True output of flip-flop 1, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature.
8 GND power_in Ground reference for the device; DC input or output voltage range is 0 V to VCC.
9 CP input Common clock input; data is captured on the positive-going edge, with clock pulse width tw of 20 ns min and fMAX of 25 MHz min at 4.5 V.
10 Q2 output True output of flip-flop 2, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature.
11 ~{Q2} output Complementary output of flip-flop 2, which is reset to logic 1 by MR.
12 D2 input Data input of flip-flop 2, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V.
13 D3 input Data input of flip-flop 3, transferred to the outputs on the positive-going clock edge with setup time tSU of 20 ns min and hold time tH of 5 ns min at 4.5 V.
14 ~{Q3} output Complementary output of flip-flop 3, which is reset to logic 1 by MR.
15 Q3 output True output of flip-flop 3, which is reset to logic 0 by MR and drives up to 10 LSTTL loads over temperature.
16 VCC power_in Supply voltage for HCT types, specified from 4.5 V to 5.5 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, HCT types VCC 4.5 5.5 V HCT types 3
Operating temperature range TA -55 125 °C 3
Input rise and fall time 500 ns VCC = 4.5 V 3
DC input or output voltage VI, VO 0 V Upper limit printed as VCC 3
DC supply voltage (absolute maximum) VCC -0.5 7 V 3
DC input diode current IIK -20 20 mA For VI < -0.5 V or VI > VCC + 0.5 V 3
DC output diode current IOK -20 20 mA For VO < -0.5 V or VO > VCC + 0.5 V 3
DC output source or sink current per output pin IO -25 25 mA For VO > -0.5 V or VO < VCC + 0.5 V 3
DC VCC or ground current ICC or IGND -50 50 mA 3
Maximum junction temperature 150 °C 3
Maximum storage temperature range -65 150 °C 3
Maximum lead temperature (soldering) 300 °C Soldering 10 s (SOIC - lead tips only) 3
High level input voltage, HCT VIH 2 V VCC = 4.5 to 5.5 V 4
Low level input voltage, HCT VIL 0.8 V VCC = 4.5 to 5.5 V 4
High level output voltage, CMOS loads VOH 4.4 V VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V 4
High level output voltage, TTL loads VOH 3.7 V IO = -4 mA; VCC = 4.5 V 4
Low level output voltage, CMOS loads VOL 0.1 V VI = VIH or VIL; IO = 0.02 mA; VCC = 4.5 V 4
Low level output voltage, TTL loads VOL 0.4 V IO = 4 mA; VCC = 4.5 V 4
Input leakage current II -1 1 µA VI = VCC to GND; IO = 0; VCC = 5.5 V 4
Quiescent device current ICC 160 µA VI = VCC or GND; IO = 0; VCC = 5.5 V 4
Additional quiescent device current per input pin, 1 unit load ∆ICC 100 490 µA VI = VCC - 2.1 V; VCC = 4.5 to 5.5 V; Note 2. Typ is 25 °C value 4
Input capacitance CIN 10 pF 5
Clock pulse width, HCT tw 30 ns VCC = 4.5 V 5
MR pulse width, HCT tw 30 ns VCC = 4.5 V 5
Setup time data to clock, HCT tSU 30 ns VCC = 4.5 V 5
Hold time data to clock, HCT tH 5 ns VCC = 4.5 V 5
Removal time MR to clock, HCT tREM 5 ns VCC = 4.5 V 5
Clock frequency, HCT fMAX 16 MHz VCC = 4.5 V 5
Propagation delay, clock to Q or Q̄, HCT tPLH, tPHL 50 ns CL = 50 pF; VCC = 4.5 V 6
Propagation delay, MR to Q or Q̄, HCT tPLH, tPHL 53 ns CL = 50 pF; VCC = 4.5 V 6
Output transition times, HCT tTLH, tTHL 22 ns CL = 50 pF; VCC = 4.5 V 6
Thermal resistance, junction to ambient, M (SOIC) package θJA 73 °C/W Typical, per JESD 51-7 (Note 1) 3

CAD (KiCad official)

  • Symbol: CD74HCT175M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct175m96-etched.step / cd74hct175m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct175m96.step / cd74hct175m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 577b40c4b30ac148, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF