CD74HCT174MT

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd74hct174mt",
  "title": "CD74HCT174MT",
  "brief": "Texas Instruments Flip Flops, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd74hct174mt"
  ],
  "component": {
    "mpn": "CD74HCT174MT",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc174",
    "parts": {
      "symbol": "cd74hct174mt.kicad_sym",
      "footprint": "cd74hct174mt.kicad_mod",
      "model_3d": "cd74hct174mt-etched.glb",
      "model_3d_plain": "cd74hct174mt.glb",
      "model_3d_step": "cd74hct174mt-etched.step",
      "model_3d_step_plain": "cd74hct174mt.step",
      "lbr": "cd74hct174mt.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "MR",
        "type": "input",
        "description": "Active-low asynchronous master reset. When driven low, all six Q outputs are forced low regardless of clock or data. Requires a minimum pulse width of 20 ns at VCC = 4.5V (HCT)."
      },
      {
        "number": "2",
        "name": "Q0",
        "type": "output",
        "description": "Q output of flip-flop 0. Latches the state of D0 on the rising edge of CP; driven low when MR is asserted low. Drives up to 10 LSTTL loads."
      },
      {
        "number": "3",
        "name": "D0",
        "type": "input",
        "description": "Data input to flip-flop 0. Sampled on the low-to-high transition of CP with the specified setup and hold times (tSU = 16 ns min, tH = 5 ns at VCC = 4.5V, HCT)."
      },
      {
        "number": "4",
        "name": "D1",
        "type": "input",
        "description": "Data input to flip-flop 1. Sampled on the low-to-high transition of CP with the specified setup and hold times."
      },
      {
        "number": "5",
        "name": "Q1",
        "type": "output",
        "description": "Q output of flip-flop 1. Latches the state of D1 on the rising edge of CP; driven low when MR is asserted low."
      },
      {
        "number": "6",
        "name": "D2",
        "type": "input",
        "description": "Data input to flip-flop 2. Sampled on the low-to-high transition of CP with the specified setup and hold times."
      },
      {
        "number": "7",
        "name": "Q2",
        "type": "output",
        "description": "Q output of flip-flop 2. Latches the state of D2 on the rising edge of CP; driven low when MR is asserted low."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device. Must be tied to the system ground."
      },
      {
        "number": "9",
        "name": "CP",
        "type": "input",
        "description": "Common clock input for all six flip-flops. Data on Dn is transferred to Qn on the low-to-high (rising) transition of CP. Minimum clock pulse width 20 ns; fMAX = 25 MHz at VCC = 4.5V (HCT)."
      },
      {
        "number": "10",
        "name": "Q3",
        "type": "output",
        "description": "Q output of flip-flop 3. Latches the state of D3 on the rising edge of CP; driven low when MR is asserted low."
      },
      {
        "number": "11",
        "name": "D3",
        "type": "input",
        "description": "Data input to flip-flop 3. Sampled on the low-to-high transition of CP with the specified setup and hold times."
      },
      {
        "number": "12",
        "name": "Q4",
        "type": "output",
        "description": "Q output of flip-flop 4. Latches the state of D4 on the rising edge of CP; driven low when MR is asserted low."
      },
      {
        "number": "13",
        "name": "D4",
        "type": "input",
        "description": "Data input to flip-flop 4. Sampled on the low-to-high transition of CP with the specified setup and hold times."
      },
      {
        "number": "14",
        "name": "D5",
        "type": "input",
        "description": "Data input to flip-flop 5. Sampled on the low-to-high transition of CP with the specified setup and hold times."
      },
      {
        "number": "15",
        "name": "Q5",
        "type": "output",
        "description": "Q output of flip-flop 5. Latches the state of D5 on the rising edge of CP; driven low when MR is asserted low."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. HCT operating range 4.5 V to 5.5 V (absolute max 7 V). Bypass with a local 0.1 uF ceramic to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hc174",
        "pages": null,
        "sha256": "b04b1439e530ada4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HCT174",
      "logic_family": "74HCT",
      "function_code": "174",
      "function_class": "Flip-Flop",
      "function_name": "Hex D Flip-Flop with Common Clock/Clear",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd74hct174mt.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd74hct174mt-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "78b0a2f1365a9b9968c611767bf4538e7dcfce8004bcc00fc2f8a39d1456de0e",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "variants": [
    {
      "mpn": "CD74HCT174MT",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTM",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTM96",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTM96E4",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTE",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTF3A",
      "kind": "packaging"
    },
    {
      "mpn": "CD74HCT174MTF",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd74hct174mt"
  ],
  "discovery_pitch": "CD74HCT174MT (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd74hct174mt.kicad_sym",
    "cd74hct174mt.kicad_mod",
    "cd74hct174mt.glb",
    "cd74hct174mt.step",
    "cd74hct174mt.lbr",
    "docs/hero.png",
    "docs/cd74hct174mt-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:57:37.631Z"
}