component
CD74HCT164E
Public Made by Adomby adom
Texas Instruments Shift Registers, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HCT164E
Texas Instruments · Shift Registers · PDIP-14
CD74HCT164E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Serial data input A, which can be used as a data enable control; HCT inputs are LSTTL compatible with VIL 0.8 V max and VIH 2 V min. |
| 2 | B | input | Serial data input B, which can be used as a data enable control; HCT inputs are LSTTL compatible with VIL 0.8 V max and VIH 2 V min. |
| 3 | QA | output | Parallel output A (first stage of the shift register), driven low by a low on CLR. |
| 4 | QB | output | Parallel output B of the shift register, driven low by a low on CLR. |
| 5 | QC | output | Parallel output C of the shift register, driven low by a low on CLR. |
| 6 | QD | output | Parallel output D of the shift register, driven low by a low on CLR. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | CLK | input | Clock input; data is shifted on the positive (low-to-high) clock edge. |
| 9 | CLR | input | Active-low asynchronous reset; a low level resets the shift register and sends all outputs low regardless of other inputs. |
| 10 | QE | output | Parallel output E of the shift register, driven low by a low on CLR. |
| 11 | QF | output | Parallel output F of the shift register, driven low by a low on CLR. |
| 12 | QG | output | Parallel output G of the shift register, driven low by a low on CLR. |
| 13 | QH | output | Parallel output H (last stage of the shift register), driven low by a low on CLR. |
| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1 µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage | VIH | 2 | V | HCT types, VCC 4.5 to 5.5 V | 5 | ||
| Low level input voltage | VIL | 0.8 | V | HCT types, VCC 4.5 to 5.5 V | 5 | ||
| High level output voltage | VOH | 4.4 | V | IOH =, 20 μA, VCC 4.5 V | 5 | ||
| High level output voltage | VOH | 3.98 | V | IOH =, 4 μA, VCC 4.5 V, 25 °C | 5 | ||
| High level output voltage | VOH | 3.84 | V | IOH =, 4 μA, VCC 4.5 V, −40 °C to 85 °C | 5 | ||
| High level output voltage | VOH | 3.7 | V | IOH =, 4 μA, VCC 4.5 V, −55 °C to 125 °C | 5 | ||
| Low level output voltage | VOL | 0.1 | V | IOL = 20 μA, VCC 4.5 V | 5 | ||
| Low level output voltage | VOL | 0.26 | V | IOL = 4 μA, VCC 4.5 V, 25 °C | 5 | ||
| Low level output voltage | VOL | 0.33 | V | IOL = 4 μA, VCC 4.5 V, −40 °C to 85 °C | 5 | ||
| Low level output voltage | VOL | 0.4 | V | IOL = 4 μA, VCC 4.5 V, −55 °C to 125 °C | 5 | ||
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND, VCC 5.5 V, 25 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND, VCC 5.5 V, −40 °C to 85 °C | 5 | |
| Supply current | ICC | 8 | μA | VI = VCC or GND, VCC 5.5 V, 25 °C | 5 | ||
| Supply current | ICC | 80 | μA | VI = VCC or GND, VCC 5.5 V, −40 °C to 85 °C | 5 | ||
| Supply current | ICC | 160 | μA | VI = VCC or GND, VCC 5.5 V, −55 °C to 125 °C | 5 | ||
| Additional supply current per input pin (Data shift-in) | ΔICC | 100 | 108 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 | |
| Additional supply current per input pin (Data shift-in) | ΔICC | 135 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 | ||
| Additional supply current per input pin (Data shift-in) | ΔICC | 147 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 | ||
| Additional supply current per input pin (CLR) | ΔICC | 100 | 324 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 | |
| Additional supply current per input pin (CLR) | ΔICC | 405 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 | ||
| Additional supply current per input pin (CLR) | ΔICC | 441 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 | ||
| Additional supply current per input pin (CLK) | ΔICC | 100 | 252 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 | |
| Additional supply current per input pin (CLK) | ΔICC | 315 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 | ||
| Additional supply current per input pin (CLK) | ΔICC | 343 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 | ||
| Supply voltage range (HCT types) | VCC | 4.5 | 5.5 | V | HCT types | 4 | |
| Input or output voltage | VI, VO | 0 | V | Upper limit is VCC (not a numeric value) | 4 | ||
| Input rise and fall time | 500 | ns | VCC = 4.5 V | 4 | |||
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (N, PDIP-14) | RθJA | 80 | °C/W | N (PDIP) package, 14 pins | 4 |
CAD (KiCad official)
- Symbol:
CD74HCT164E - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hct164e-etched.step/cd74hct164e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct164e.step/cd74hct164e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
daeb5979b51ad973, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HCT164E
**Texas Instruments** · Shift Registers · PDIP-14
CD74HCT164E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Serial data input A, which can be used as a data enable control; HCT inputs are LSTTL compatible with VIL 0.8 V max and VIH 2 V min. |
| 2 | B | input | Serial data input B, which can be used as a data enable control; HCT inputs are LSTTL compatible with VIL 0.8 V max and VIH 2 V min. |
| 3 | QA | output | Parallel output A (first stage of the shift register), driven low by a low on CLR. |
| 4 | QB | output | Parallel output B of the shift register, driven low by a low on CLR. |
| 5 | QC | output | Parallel output C of the shift register, driven low by a low on CLR. |
| 6 | QD | output | Parallel output D of the shift register, driven low by a low on CLR. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | CLK | input | Clock input; data is shifted on the positive (low-to-high) clock edge. |
| 9 | CLR | input | Active-low asynchronous reset; a low level resets the shift register and sends all outputs low regardless of other inputs. |
| 10 | QE | output | Parallel output E of the shift register, driven low by a low on CLR. |
| 11 | QF | output | Parallel output F of the shift register, driven low by a low on CLR. |
| 12 | QG | output | Parallel output G of the shift register, driven low by a low on CLR. |
| 13 | QH | output | Parallel output H (last stage of the shift register), driven low by a low on CLR. |
| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V for HCT types, with a 0.1 µF bypass capacitor recommended close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage | VIH | 2 | | | V | HCT types, VCC 4.5 to 5.5 V | 5 |
| Low level input voltage | VIL | | | 0.8 | V | HCT types, VCC 4.5 to 5.5 V | 5 |
| High level output voltage | VOH | 4.4 | | | V | IOH =, 20 μA, VCC 4.5 V | 5 |
| High level output voltage | VOH | 3.98 | | | V | IOH =, 4 μA, VCC 4.5 V, 25 °C | 5 |
| High level output voltage | VOH | 3.84 | | | V | IOH =, 4 μA, VCC 4.5 V, −40 °C to 85 °C | 5 |
| High level output voltage | VOH | 3.7 | | | V | IOH =, 4 μA, VCC 4.5 V, −55 °C to 125 °C | 5 |
| Low level output voltage | VOL | | | 0.1 | V | IOL = 20 μA, VCC 4.5 V | 5 |
| Low level output voltage | VOL | | | 0.26 | V | IOL = 4 μA, VCC 4.5 V, 25 °C | 5 |
| Low level output voltage | VOL | | | 0.33 | V | IOL = 4 μA, VCC 4.5 V, −40 °C to 85 °C | 5 |
| Low level output voltage | VOL | | | 0.4 | V | IOL = 4 μA, VCC 4.5 V, −55 °C to 125 °C | 5 |
| Input leakage current | II | -0.1 | | 0.1 | μA | VI = VCC or GND, VCC 5.5 V, 25 °C | 5 |
| Input leakage current | II | -1 | | 1 | μA | VI = VCC or GND, VCC 5.5 V, −40 °C to 85 °C | 5 |
| Supply current | ICC | | | 8 | μA | VI = VCC or GND, VCC 5.5 V, 25 °C | 5 |
| Supply current | ICC | | | 80 | μA | VI = VCC or GND, VCC 5.5 V, −40 °C to 85 °C | 5 |
| Supply current | ICC | | | 160 | μA | VI = VCC or GND, VCC 5.5 V, −55 °C to 125 °C | 5 |
| Additional supply current per input pin (Data shift-in) | ΔICC | | 100 | 108 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 |
| Additional supply current per input pin (Data shift-in) | ΔICC | | | 135 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 |
| Additional supply current per input pin (Data shift-in) | ΔICC | | | 147 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 |
| Additional supply current per input pin (CLR) | ΔICC | | 100 | 324 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 |
| Additional supply current per input pin (CLR) | ΔICC | | | 405 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 |
| Additional supply current per input pin (CLR) | ΔICC | | | 441 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 |
| Additional supply current per input pin (CLK) | ΔICC | | 100 | 252 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, 25 °C | 5 |
| Additional supply current per input pin (CLK) | ΔICC | | | 315 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −40 °C to 85 °C | 5 |
| Additional supply current per input pin (CLK) | ΔICC | | | 343 | μA | VCC 4.5 to 5.5 V, per input at TTL level, inputs at VCC, 2.1 V, −55 °C to 125 °C | 5 |
| Supply voltage range (HCT types) | VCC | 4.5 | | 5.5 | V | HCT types | 4 |
| Input or output voltage | VI, VO | 0 | | | V | Upper limit is VCC (not a numeric value) | 4 |
| Input rise and fall time | | | | 500 | ns | VCC = 4.5 V | 4 |
| Temperature range | TA | -55 | | 125 | °C | | 4 |
| Supply voltage range | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -25 | | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -50 | | 50 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Junction-to-ambient thermal resistance (N, PDIP-14) | RθJA | | 80 | | °C/W | N (PDIP) package, 14 pins | 4 |
## CAD (KiCad official)
- Symbol: `CD74HCT164E`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `cd74hct164e-etched.step` / `cd74hct164e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct164e.step` / `cd74hct164e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct164) (24 pp, sha256 `daeb5979b51ad973`, retrieved 2026-10-15, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hct164e-datasheet.pdf)