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CD74HCT163M96

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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT163M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74HCT163M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input; a low level resets all counter outputs, and for the '163 types the reset is synchronous, occurring regardless of the SPE, PE and TE levels.
2 CP input Clock input; counting and parallel presetting occur on the negative-to-positive (low-to-high) transition of CP.
3 P0 input Parallel preset data input for bit 0, loaded into the counter when SPE is low and the setup and hold requirements are met.
4 P1 input Parallel preset data input for bit 1, loaded into the counter when SPE is low and the setup and hold requirements are met.
5 P2 input Parallel preset data input for bit 2, loaded into the counter when SPE is low and the setup and hold requirements are met.
6 P3 input Parallel preset data input for bit 3, loaded into the counter when SPE is low and the setup and hold requirements are met.
7 PE input Count enable input (one of two for cascading); both PE and TE must be high for the counter to count.
8 GND power_in Device ground; the datasheet specifies input and output voltages between 0 V and VCC.
9 SPE input Synchronous parallel enable; a low level disables counting and allows data at P0 to P3 to be loaded on the clock edge.
10 TE input Count enable input (second of two for cascading); gated with the Q outputs to generate TC, and both PE and TE must be high to count.
11 Q3 output Counter output bit 3 (most significant bit).
12 Q2 output Counter output bit 2.
13 Q1 output Counter output bit 1.
14 Q0 output Counter output bit 0 (least significant bit).
15 TC output Terminal count output that goes high for one clock period when TE is high and the counter is at terminal count (HHHH), used to enable the next cascaded stage.
16 VCC power_in Supply voltage; HCT types operate from 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range, HCT types VCC 4.5 5.5 V HCT types 4
Operating temperature range TA -55 125 °C 4
Input rise and fall time 500 ns VCC = 4.5 V 4
DC supply voltage VCC -0.5 7 V 4
DC input diode current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 4
DC output diode current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 4
DC drain current, per output IO -25 25 mA For -0.5V < VO < VCC + 0.5V 4
DC output source or sink current per output pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V 4
DC VCC or ground current ICC -50 50 mA 4
Storage temperature range -65 150 °C 4
Maximum junction temperature 150 °C 4
Maximum lead temperature (soldering) 300 °C 10 s; SOIC lead tips only 4
High level input voltage VIH 2 V VCC = 4.5 to 5.5 V; TA = 25°C 5
Low level input voltage VIL 0.8 V VCC = 4.5 to 5.5 V; TA = 25°C 5
High level output voltage, CMOS loads VOH 4.4 V VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V; TA = 25°C 5
High level output voltage, TTL loads VOH 3.98 V IO = -4 mA; VCC = 4.5 V; TA = 25°C 5
High level output voltage, TTL loads VOH 3.7 V IO = -4 mA; VCC = 4.5 V; TA = -55°C to 125°C 5
Low level output voltage, CMOS loads VOL 0.1 V VI = VIH or VIL; IO = 0.02 mA; VCC = 4.5 V; TA = 25°C 5
Low level output voltage, TTL loads VOL 0.26 V IO = 4 mA; VCC = 4.5 V; TA = 25°C 5
Low level output voltage, TTL loads VOL 0.4 V IO = 4 mA; VCC = 4.5 V; TA = -55°C to 125°C 5
Input leakage current II -0.1 0.1 µA VI = VCC and GND; IO = 0 mA; VCC = 5.5 V; TA = 25°C 5
Input leakage current II -1 1 µA VI = VCC and GND; IO = 0 mA; VCC = 5.5 V; TA = -55°C to 125°C 5
Quiescent device current ICC 8 µA VI = VCC or GND; IO = 0 mA; VCC = 5.5 V; TA = 25°C 5
Quiescent device current ICC 160 µA VI = VCC or GND; IO = 0 mA; VCC = 5.5 V; TA = -55°C to 125°C 5
Additional quiescent device current per input pin, 1 unit load ΔICC 100 360 µA VI = VCC - 2.1 V; VCC = 4.5 to 5.5 V; TA = 25°C 5
Additional quiescent device current per input pin, 1 unit load ΔICC 490 µA VI = VCC - 2.1 V; VCC = 4.5 to 5.5 V; TA = -55°C to 125°C 5
Maximum CP frequency fMAX 30 MHz VCC = 4.5 V; TA = 25°C; non-cascaded operation (Note 6) 7
Maximum CP frequency fMAX 20 MHz VCC = 4.5 V; TA = -55°C to 125°C; non-cascaded operation (Note 6) 7
CP width (low) tW(L) 16 ns VCC = 4.5 V; TA = 25°C 7
CP width (low) tW(L) 24 ns VCC = 4.5 V; TA = -55°C to 125°C 7
Setup time, Pn to CP tSU 10 ns VCC = 4.5 V; TA = 25°C 7
Setup time, Pn to CP tSU 15 ns VCC = 4.5 V; TA = -55°C to 125°C 7
Setup time, PE or TE to CP tSU 13 ns VCC = 4.5 V; TA = 25°C 7
Setup time, PE or TE to CP tSU 20 ns VCC = 4.5 V; TA = -55°C to 125°C 7
Setup time, SPE to CP tSU 12 ns VCC = 4.5 V; TA = 25°C 7
Setup time, SPE to CP tSU 18 ns VCC = 4.5 V; TA = -55°C to 125°C 7
Setup time, MR to CP (163) tSU 13 ns VCC = 4.5 V; TA = 25°C 7
Setup time, MR to CP (163) tSU 20 ns VCC = 4.5 V; TA = -55°C to 125°C 7
Hold time, Pn to CP tH 5 ns VCC = 4.5 V; TA = 25°C 7
Hold time, TE or PE to CP tH 3 ns VCC = 4.5 V; TA = 25°C 7
Hold time, SPE to CP tH 3 ns VCC = 4.5 V; TA = 25°C 7
Propagation delay, CP to TC tPHL, tPLH 42 ns CL = 50pF; VCC = 4.5 V; TA = 25°C 8
Propagation delay, CP to TC tPHL, tPLH 63 ns CL = 50pF; VCC = 4.5 V; TA = -55°C to 125°C 8
Propagation delay, CP to Qn tPHL, tPLH 39 ns CL = 50pF; VCC = 4.5 V; TA = 25°C 8
Propagation delay, CP to Qn tPHL, tPLH 59 ns CL = 50pF; VCC = 4.5 V; TA = -55°C to 125°C 8
Propagation delay, TE to TC tPHL, tPLH 32 ns CL = 50pF; VCC = 4.5 V; TA = 25°C 8
Propagation delay, TE to TC tPHL, tPLH 48 ns CL = 50pF; VCC = 4.5 V; TA = -55°C to 125°C 8
Output transition time tTHL, tTLH 15 ns CL = 50pF; VCC = 4.5 V; TA = 25°C 8
Output transition time tTHL, tTLH 22 ns CL = 50pF; VCC = 4.5 V; TA = -55°C to 125°C 8
Thermal resistance, junction to ambient, M (SOIC) package θJA 73 °C/W Typical, Note 4 (JESD 51-7) 4

CAD (KiCad official)

  • Symbol: CD74HCT163M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct163m96-etched.step / cd74hct163m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct163m96.step / cd74hct163m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 bd5247f3f54329d0, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF