CD74HCT161M96

{
  "slug": "cd74hct161m96",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "cd74hct161m96",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
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    "cd74hct161m96.step",
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    "docs/cd74hct161m96-datasheet.pdf",
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  "component": {
    "mpn": "CD74HCT161M96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Counters, Dividers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc161",
    "parts": {
      "symbol": "cd74hct161m96.kicad_sym",
      "footprint": "cd74hct161m96.kicad_mod",
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      "model_3d_plain": "cd74hct161m96.glb",
      "model_3d_step": "cd74hct161m96-etched.step",
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      "lbr": "cd74hct161m96.lbr"
    },
    "distributor_links": {
      "lcsc": "C2653005",
      "digikey": "296-38073-2-ND",
      "mouser": "595-CD74HCT161M96"
    },
    "distributor_check": {
      "checked_at": "2026-10-12T04:25:20Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-38073-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-CD74HCT161M96",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "MR",
        "type": "input",
        "description": "Master Reset input; a low level resets all counter outputs regardless of the levels on SPE, PE and TE."
      },
      {
        "number": "2",
        "name": "CP",
        "type": "input",
        "description": "Clock input; counting and parallel presetting occur on the negative-to-positive clock transition, and on the '161 type reset is asynchronous with CP."
      },
      {
        "number": "3",
        "name": "P0",
        "type": "input",
        "description": "Parallel data input bit 0, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25)."
      },
      {
        "number": "4",
        "name": "P1",
        "type": "input",
        "description": "Parallel data input bit 1, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25)."
      },
      {
        "number": "5",
        "name": "P2",
        "type": "input",
        "description": "Parallel data input bit 2, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25)."
      },
      {
        "number": "6",
        "name": "P3",
        "type": "input",
        "description": "Parallel data input bit 3, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25)."
      },
      {
        "number": "7",
        "name": "PE",
        "type": "input",
        "description": "Count enable (parallel enable) input for n-bit cascading; both PE and TE must be high for the counter to count."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "9",
        "name": "SPE",
        "type": "input",
        "description": "Synchronous parallel enable; a low level disables counting and allows data at P0 to P3 to be loaded on the clock edge (HCT unit load 0.5)."
      },
      {
        "number": "10",
        "name": "TE",
        "type": "input",
        "description": "Count enable (terminal count enable) input for cascading; gated with the Q outputs so TC goes high for one clock period at maximum count when TE is high."
      },
      {
        "number": "11",
        "name": "Q3",
        "type": "output",
        "description": "Counter output for bit 3 of the 4-bit count, changing on the clock transition when counting or loading."
      },
      {
        "number": "12",
        "name": "Q2",
        "type": "output",
        "description": "Counter output for bit 2 of the 4-bit count, changing on the clock transition when counting or loading."
      },
      {
        "number": "13",
        "name": "Q1",
        "type": "output",
        "description": "Counter output for bit 1 of the 4-bit count, changing on the clock transition when counting or loading."
      },
      {
        "number": "14",
        "name": "Q0",
        "type": "output",
        "description": "Counter output for bit 0 of the 4-bit count, changing on the clock transition when counting or loading."
      },
      {
        "number": "15",
        "name": "TC",
        "type": "output",
        "description": "Terminal count output; goes high when TE is high and the counter is at terminal count (HHHH), for one clock period, to enable the next cascaded stage."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; HCT types operate from 4.5 V to 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pinout drawing text on page 2 does not show a clean number-to-name table. Pin numbers were mappe; The datasheet pinout is shared by the CERDIP, PDIP and SOIC packages, and the SOIC variant is given ; The datasheet does not state which of Q0-Q3 is the most significant bit in words; the descriptions f"
        ],
        "pages_sent": 20,
        "cost_usd": 0.0888,
        "at": "2026-10-12T04:25:06"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hc161",
        "pages": 20,
        "sha256": "cfdc63695252f714",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "f15830f236a03cffbad716b1d295c5c18720777857f7f37fd4b9d43dcf9263e7",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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}