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CD74HCT161M96

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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT161M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74HCT161M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master Reset input; a low level resets all counter outputs regardless of the levels on SPE, PE and TE.
2 CP input Clock input; counting and parallel presetting occur on the negative-to-positive clock transition, and on the '161 type reset is asynchronous with CP.
3 P0 input Parallel data input bit 0, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25).
4 P1 input Parallel data input bit 1, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25).
5 P2 input Parallel data input bit 2, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25).
6 P3 input Parallel data input bit 3, loaded into the counter when SPE is low, subject to SPE setup and hold times (HCT unit load 0.25).
7 PE input Count enable (parallel enable) input for n-bit cascading; both PE and TE must be high for the counter to count.
8 GND power_in Ground reference for the device.
9 SPE input Synchronous parallel enable; a low level disables counting and allows data at P0 to P3 to be loaded on the clock edge (HCT unit load 0.5).
10 TE input Count enable (terminal count enable) input for cascading; gated with the Q outputs so TC goes high for one clock period at maximum count when TE is high.
11 Q3 output Counter output for bit 3 of the 4-bit count, changing on the clock transition when counting or loading.
12 Q2 output Counter output for bit 2 of the 4-bit count, changing on the clock transition when counting or loading.
13 Q1 output Counter output for bit 1 of the 4-bit count, changing on the clock transition when counting or loading.
14 Q0 output Counter output for bit 0 of the 4-bit count, changing on the clock transition when counting or loading.
15 TC output Terminal count output; goes high when TE is high and the counter is at terminal count (HHHH), for one clock period, to enable the next cascaded stage.
16 VCC power_in Supply voltage; HCT types operate from 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HCT161M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct161m96-etched.step / cd74hct161m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct161m96.step / cd74hct161m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 cfdc63695252f714, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF