component

CD74HCT137M96

Public Made by Adom

by adom

Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hct137m96factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd74hct137m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hct137m96: viewers · Ray
cd74hct137m96-etched.fit.json cd74hct137m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hct137m96-etched.glb cd74hct137m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
cd74hct137m96-etched.step cd74hct137m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
cd74hct137m96.glb Publish 0.1.0 · Ray
cd74hct137m96.kicad_mod Publish 0.1.0 · Ray
cd74hct137m96.kicad_sym Publish 0.1.0 · Ray
cd74hct137m96.lbr Publish 0.1.0 · Ray
cd74hct137m96.step Publish 0.1.0 · Ray
package.json cd74hct137m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
page.json cd74hct137m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
README.md Initial commit: component/cd74hct137m96 · Ray

CD74HCT137M96

Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16

CD74HCT137M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Binary address select input 0; combined with A1 and A2 selects one of eight outputs; all inputs accept LSTTL-compatible levels (VIH ≥ 2 V, VIL ≤ 0.8 V at VCC = 4.5-5.5 V).
2 A1 input Binary address select input 1; combined with A0 and A2 selects one of eight outputs; can be latched by LE.
3 A2 input Binary address select input 2; combined with A0 and A1 selects one of eight outputs; can be latched by LE.
4 LE input Latch Enable input; active HIGH latches address inputs A0-A2 isolating outputs from subsequent address changes; LOW makes outputs transparent to address inputs.
5 OE1 input Output Enable 1 input (active LOW); HIGH forces all Y outputs inactive (HIGH); must be LOW together with OE0 HIGH to enable decoding.
6 OE0 input Output Enable 0 input (active HIGH); LOW forces all Y outputs inactive (HIGH); must be HIGH together with OE1 LOW to enable decoding.
7 Y7 output Active-LOW decoded output 7; LOW when A2=H, A1=H, A0=H, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA, VOL ≤ 0.4 V at IOL = 4 mA.
8 GND power_in Ground supply reference, 0 V; maximum DC VCC or ground current ±50 mA.
9 Y6 output Active-LOW decoded output 6; LOW when A2=H, A1=H, A0=L, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
10 Y5 output Active-LOW decoded output 5; LOW when A2=H, A1=L, A0=H, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
11 Y4 output Active-LOW decoded output 4; LOW when A2=H, A1=L, A0=L, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
12 Y3 output Active-LOW decoded output 3; LOW when A2=L, A1=H, A0=H, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
13 Y2 output Active-LOW decoded output 2; LOW when A2=L, A1=H, A0=L, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
14 Y1 output Active-LOW decoded output 1; LOW when A2=L, A1=L, A0=H, LE=L, OE0=H, OE1=L; max output sink/source current ±25 mA.
15 Y0 output Active-LOW decoded output 0; LOW when A2=L, A1=L, A0=L, LE=L, OE0=H, OE1=L; propagation delay tPLH/tPHL ≤ 38 ns at VCC = 4.5 V, CL = 50 pF, 25 °C.
16 VCC power_in Positive supply voltage; 4.5 V to 5.5 V operating range for HCT type; quiescent supply current ICC ≤ 8 µA typical, 80 µA max at 25 °C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HCT137M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hct137m96-etched.step / cd74hct137m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct137m96.step / cd74hct137m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 ed9eabdb879f73d9, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF