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CD74HCT126M96

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hct126m96factory-2.0.0extractor-text

Verified CD74HCT126M96

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HCT126M96 · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 27-page datasheet
  • ✓distributor: lcsc C2675949, digikey 296-14546-2-ND, mouser 595-CD74HCT126M96
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1yao1hrp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hct126m96.kicad_sym✓ cd74hct126m96.kicad_mod✓ cd74hct126m96.step
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CD74HCT126M96

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-14

CD74HCT126M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Channel 1 output enable: when high the buffer drives Y from A, and when low the output 1Y is in the high-impedance (Z) state.
2 1A input Channel 1 data input A, a TTL-compatible CMOS input with VIH(min) of 2 V and VIL(max) of 0.8 V at VCC = 4.5 V to 5.5 V.
3 1Y output Channel 1 3-state buffer output Y, equal to A when 1OE is high and high-impedance when disabled.
4 2OE input Channel 2 output enable: when high the buffer drives Y from A, and when low the output 2Y is in the high-impedance (Z) state.
5 2A input Channel 2 data input A, a TTL-compatible CMOS input with VIH(min) of 2 V and VIL(max) of 0.8 V at VCC = 4.5 V to 5.5 V.
6 2Y output Channel 2 3-state buffer output Y, equal to A when 2OE is high and high-impedance when disabled.
7 GND power_in Ground reference for the device.
8 3Y output Channel 3 3-state buffer output Y, equal to A when 3OE is high and high-impedance when disabled.
9 3A input Channel 3 data input A, a TTL-compatible CMOS input with VIH(min) of 2 V and VIL(max) of 0.8 V at VCC = 4.5 V to 5.5 V.
10 3OE input Channel 3 output enable: when high the buffer drives Y from A, and when low the output 3Y is in the high-impedance (Z) state.
11 4Y output Channel 4 3-state buffer output Y, equal to A when 4OE is high and high-impedance when disabled.
12 4A input Channel 4 data input A, a TTL-compatible CMOS input with VIH(min) of 2 V and VIL(max) of 0.8 V at VCC = 4.5 V to 5.5 V.
13 4OE input Channel 4 output enable: when high the buffer drives Y from A, and when low the output 4Y is in the high-impedance (Z) state.
14 VCC power_in Positive supply, specified for 4.5 V to 5.5 V operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input transition time tt 500 ns VCC = 4.5 V 4
Input transition time tt 400 ns VCC = 5.5 V 4
Operating free-air temperature TA -55 125 °C 4
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -35 35 mA VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Lead temperature (soldering 10s) 300 °C SOIC - lead tips only 4
Storage temperature Tstg -65 150 °C 4
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -20 µA, VCC 4.5 V, TA -55°C to 125°C 5
High-level output voltage VOH 3.7 V VI = VIH or VIL, IOH = -4 mA, VCC 4.5 V, TA -55°C to 125°C 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC 4.5 V, TA -55°C to 125°C 5
Low-level output voltage VOL 0.4 V VI = VIH or VIL, IOL = 4 mA, VCC 4.5 V, TA -55°C to 125°C 5
Input leakage current II -1 1 µA VI = VCC and GND, IO = 0, VCC 5.5 V, TA -55°C to 125°C 5
Three-state leakage current IOZ -10 10 µA VI = VIH or VIL, VCC 5.5 V, TA -55°C to 125°C 5
Supply current ICC 160 µA VI = VCC or GND, IO = 0, VCC 5.5 V, TA -55°C to 125°C 5
Additional Quiescent Device Current per input pin ΔICC 490 µA VI = VCC, 2.1 V, VCC 4.5 V to 5.5 V, TA -55°C to 125°C 5
Input capacitance Ci 10 pF 5
Three-state output capacitance Co 20 pF 5
Propagation delay A to Y tpd 36 ns CL = 50 pF, VCC 4.5 V, TA -55°C to 125°C 5
Propagation delay A to Y tpd 9 ns CL = 15 pF, VCC 5 V 5
Enable delay OE to Y ten 38 ns CL = 50 pF, VCC 4.5 V, TA -55°C to 125°C 5
Enable delay OE to Y ten 10 ns CL = 15 pF, VCC 5 V 5
Disable delay OE to Y tdis 42 ns CL = 50 pF, VCC 4.5 V, TA -55°C to 125°C 5
Disable delay OE to Y tdis 11 ns CL = 15 pF, VCC 5 V 5
Transition-time Y tt 18 ns CL = 50 pF, VCC 4.5 V, TA -55°C to 125°C 5
Power dissipation capacitance per gate Cpd 36 pF No load, VCC 5 V 5
Junction-to-ambient thermal resistance (D, SOIC) RθJA 96.7 °C/W 4
Junction-to-case (top) thermal resistance (D, SOIC) RθJC(top) 53.3 °C/W 4
Junction-to-board thermal resistance (D, SOIC) RθJB 52.4 °C/W 4
Junction-to-top characterization parameter (D, SOIC) ΨJT 15.8 °C/W 4
Junction-to-board characterization parameter (D, SOIC) ΨJB 52.1 °C/W 4

CAD (KiCad official)

  • Symbol: CD74HCT126M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hct126m96-etched.step / cd74hct126m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct126m96.step / cd74hct126m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 25bfc54b86e7c16f, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF