Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	1d ago
viewers	cd74hct10m: viewers · Ray	1d ago
cd74hct10m-etched.glb	cd74hct10m: factory component page (tier=lcsc) · Ray	1d ago
cd74hct10m-etched.step	cd74hct10m: factory component page (tier=lcsc) · Ray	1d ago
cd74hct10m-hero.glb	cd74hct10m: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
cd74hct10m-hero.overlay.json	Publish 0.1.0 · Ray	1d ago
cd74hct10m.glb	Publish 0.1.0 · Ray	1d ago
cd74hct10m.kicad_mod	Publish 0.1.0 · Ray	1d ago
cd74hct10m.kicad_sym	Publish 0.1.0 · Ray	1d ago
cd74hct10m.lbr	Publish 0.1.0 · Ray	1d ago
cd74hct10m.step	Publish 0.1.0 · Ray	1d ago
package.json	Publish 0.1.0 · Ray	1d ago
page.json	Set visibility: public · Ray	1d ago
README.md	Initial commit: component/cd74hct10m · Ray	1d ago

CD74HCT10M

Texas Instruments · Logic Gates · SOIC-14

CD74HCT10M from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Channel 1 input A of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
2	1B	input	Channel 1 input B of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V, and unused inputs must be tied to VCC or GND.
3	2A	input	Channel 2 input A of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
4	2B	input	Channel 2 input B of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V, and unused inputs must be tied to VCC or GND.
5	2C	input	Channel 2 input C of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
6	2Y	output	Channel 2 output Y of the NAND gate (Y = A·B·C); it is a balanced CMOS push-pull output that should not be connected directly to VCC or ground.
7	GND	power_in	Ground reference for the device; all outputs sink current through this pin, and the total current through GND or VCC must not exceed ±50 mA.
8	3Y	output	Channel 3 output Y of the NAND gate (Y = A·B·C); it is a balanced CMOS push-pull output that should not be connected directly to VCC or ground.
9	3A	input	Channel 3 input A of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
10	3B	input	Channel 3 input B of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V, and unused inputs must be tied to VCC or GND.
11	3C	input	Channel 3 input C of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
12	1Y	output	Channel 1 output Y of the NAND gate (Y = A·B·C); it is a balanced CMOS push-pull output that should not be connected directly to VCC or ground.
13	1C	input	Channel 1 input C of the 3-input NAND gate; as a TTL-compatible CMOS input it requires VIH of at least 2 V and VIL of at most 0.8 V at VCC = 4.5 V to 5.5 V.
14	VCC	power_in	Positive supply, specified for 4.5 V to 5.5 V (absolute maximum 7 V), with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: CD74HCT10M
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: cd74hct10m-etched.step / cd74hct10m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct10m.step / cd74hct10m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 f4f5da8fe225e38c, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF