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CD74HCT08M96

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HCT08M96

Texas Instruments · Logic Gates · SOIC-14

CD74HCT08M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of gate 1 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
2 1B input Input B of gate 1 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
3 1Y output Output Y of gate 1, Y = A AND B, driven as a balanced CMOS push-pull output.
4 2A input Input A of gate 2 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
5 2B input Input B of gate 2 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
6 2Y output Output Y of gate 2, Y = A AND B, driven as a balanced CMOS push-pull output.
7 GND power_in Ground reference for the device; the datasheet requires the continuous current through VCC or GND to stay within ±50 mA.
8 3Y output Output Y of gate 3, Y = A AND B, driven as a balanced CMOS push-pull output.
9 3A input Input A of gate 3 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
10 3B input Input B of gate 3 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
11 4Y output Output Y of gate 4, Y = A AND B, driven as a balanced CMOS push-pull output.
12 4A input Input A of gate 4 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
13 4B input Input B of gate 4 (2-input AND); VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V, with rise/fall rate limited to 500 ns at 4.5 V.
14 VCC power_in Positive supply; recommended range 4.5 V to 5.5 V, absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD74HCT08M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hct08m96-etched.step / cd74hct08m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct08m96.step / cd74hct08m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 55370b959c9d42a8, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF