component
CD74HCT04E
Public Made by Adomby adom
Texas Instruments Inverters, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HCT04E
Texas Instruments · Inverters · PDIP-14
CD74HCT04E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 2 | 1Y | output | Channel 1 inverter output Y, which is the logical inverse of input 1A. |
| 3 | 2A | input | Channel 2 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 4 | 2Y | output | Channel 2 inverter output Y, which is the logical inverse of input 2A. |
| 5 | 3A | input | Channel 3 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 6 | 3Y | output | Channel 3 inverter output Y, which is the logical inverse of input 3A. |
| 7 | GND | power_in | Ground reference for the device, to be connected to the system ground. |
| 8 | 4Y | output | Channel 4 inverter output Y, which is the logical inverse of input 4A. |
| 9 | 4A | input | Channel 4 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 10 | 5Y | output | Channel 5 inverter output Y, which is the logical inverse of input 5A. |
| 11 | 5A | input | Channel 5 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 12 | 6Y | output | Channel 6 inverter output Y, which is the logical inverse of input 6A. |
| 13 | 6A | input | Channel 6 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 14 | VCC | power_in | Positive supply, operating from 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD74HCT04E - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hct04e-etched.step/cd74hct04e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct04e.step/cd74hct04e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
ef067fe4243d0e51, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HCT04E
**Texas Instruments** · Inverters · PDIP-14
CD74HCT04E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 2 | 1Y | output | Channel 1 inverter output Y, which is the logical inverse of input 1A. |
| 3 | 2A | input | Channel 2 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 4 | 2Y | output | Channel 2 inverter output Y, which is the logical inverse of input 2A. |
| 5 | 3A | input | Channel 3 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 6 | 3Y | output | Channel 3 inverter output Y, which is the logical inverse of input 3A. |
| 7 | GND | power_in | Ground reference for the device, to be connected to the system ground. |
| 8 | 4Y | output | Channel 4 inverter output Y, which is the logical inverse of input 4A. |
| 9 | 4A | input | Channel 4 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 10 | 5Y | output | Channel 5 inverter output Y, which is the logical inverse of input 5A. |
| 11 | 5A | input | Channel 5 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 12 | 6Y | output | Channel 6 inverter output Y, which is the logical inverse of input 6A. |
| 13 | 6A | input | Channel 6 inverter input A, which accepts VIH min 2 V and VIL max 0.8 V at VCC 4.5 V to 5.5 V. |
| 14 | VCC | power_in | Positive supply, operating from 4.5 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `CD74HCT04E`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `cd74hct04e-etched.step` / `cd74hct04e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hct04e.step` / `cd74hct04e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hct04e.pdf) (28 pp, sha256 `ef067fe4243d0e51`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hct04e-datasheet.pdf)