component
CD74HC85M96
Public Made by Adomby adom
Texas Instruments Logic ICs, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HC85M96
Texas Instruments · Logic ICs · SOP-16
CD74HC85M96 from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B3 | input | Most significant bit of 4-bit word B, a comparing input. |
| 2 | (A < B) IN | input | Cascading input for the A less than B result from a preceding stage, used for serial or parallel expansion. |
| 3 | (A = B) IN | input | Cascading input for the A equals B result from a preceding stage, used for serial or parallel expansion. |
| 4 | (A > B) IN | input | Cascading input for the A greater than B result from a preceding stage, used for serial or parallel expansion. |
| 5 | (A > B) OUT | output | Buffered output that goes high when word A is greater than word B. |
| 6 | (A = B) OUT | output | Buffered output that goes high when word A equals word B. |
| 7 | (A < B) OUT | output | Buffered output that goes high when word A is less than word B. |
| 8 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±50 mA. |
| 9 | B0 | input | Least significant bit of 4-bit word B, a comparing input. |
| 10 | A0 | input | Least significant bit of 4-bit word A, a comparing input. |
| 11 | B1 | input | Bit 1 of 4-bit word B, a comparing input. |
| 12 | A1 | input | Bit 1 of 4-bit word A, a comparing input. |
| 13 | A2 | input | Bit 2 of 4-bit word A, a comparing input. |
| 14 | B2 | input | Bit 2 of 4-bit word B, a comparing input. |
| 15 | A3 | input | Most significant bit of 4-bit word A, a comparing input. |
| 16 | VCC | power_in | Supply voltage of 2 V to 6 V for HC types, with a 0.1-µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (HC types) | VCC | 2 | 6 | V | HC types | 4 | |
| Input or output voltage | VI, VO | 0 | V | Maximum is VCC | 4 | ||
| Input rise and fall time | 1000 | ns | VCC = 2 V | 4 | |||
| Input rise and fall time | 500 | ns | VCC = 4.5 V | 4 | |||
| Input rise and fall time | 400 | ns | VCC = 6 V | 4 | |||
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input diode current | IIK | -20 | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output diode current | IOK | -20 | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output source or sink current per output pin | IO | -25 | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | ICC | -50 | 50 | mA | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature | 300 | °C | Soldering 10 s (SOIC - lead tips only) | 4 | |||
| Junction-to-ambient thermal resistance | RθJA | 73 | °C/W | D (SOIC) 16-pin package | 4 | ||
| High level input voltage | VIH | 1.5 | V | VCC = 2 V | 5 | ||
| High level input voltage | VIH | 3.15 | V | VCC = 4.5 V | 5 | ||
| High level input voltage | VIH | 4.2 | V | VCC = 6 V | 5 | ||
| Low level input voltage | VIL | 0.5 | V | VCC = 2 V | 5 | ||
| Low level input voltage | VIL | 1.35 | V | VCC = 4.5 V | 5 | ||
| Low level input voltage | VIL | 1.8 | V | VCC = 6 V | 5 | ||
| High level output voltage | VOH | 1.9 | V | IOH = -20 μA; VCC = 2 V | 5 | ||
| High level output voltage | VOH | 4.4 | V | IOH = -20 μA; VCC = 4.5 V | 5 | ||
| High level output voltage | VOH | 5.9 | V | IOH = -20 μA; VCC = 6 V | 5 | ||
| High level output voltage | VOH | 3.98 | V | IOH = -4 mA; VCC = 4.5 V; 25°C | 5 | ||
| High level output voltage | VOH | 5.48 | V | IOH = -5.2 mA; VCC = 6 V; 25°C | 5 | ||
| Low level output voltage | VOL | 0.1 | V | IOL = 20 μA; VCC = 2 V | 5 | ||
| Low level output voltage | VOL | 0.26 | V | IOL = 4 mA; VCC = 4.5 V; 25°C | 5 | ||
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6 V; TA = -55 to 125°C | 5 | |
| Supply current | ICC | 8 | 80 | μA | VI = VCC or GND; VCC = 6 V; 25°C | 5 | |
| Supply current | ICC | 160 | μA | VI = VCC or GND; VCC = 6 V; TA = -55 to 125°C | 5 | ||
| Propagation delay An, Bn to (A > B) OUT, (A < B) OUT | tPLH, tPHL | 295 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 | ||
| Propagation delay An, Bn to (A = B) OUT | tPLH, tPHL | 265 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 | ||
| Propagation delay (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT | tPLH, tPHL | 210 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 | ||
| Propagation delay (A > B) IN to (A = B) OUT | tPLH, tPHL | 180 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 | ||
| Propagation delay An, Bn to (A > B) OUT, (A < B) OUT | tPLH, tPHL | 50 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 | ||
| Propagation delay An, Bn to (A = B) OUT | tPLH, tPHL | 45 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 | ||
| Propagation delay (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT | tPLH, tPHL | 36 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 | ||
| Propagation delay (A > B) IN to (A = B) OUT | tPLH, tPHL | 31 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 | ||
| Output transition times | tTLH, tTHL | 110 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 | ||
| Output transition times | tTLH, tTHL | 19 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 | ||
| Input capacitance | CIN | 10 | pF | 6 | |||
| Power dissipation capacitance | CPD | 24 | pF | VCC = 5 V | 6 |
CAD (KiCad official)
- Symbol:
CD74HC85M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hc85m96-etched.step/cd74hc85m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc85m96.step/cd74hc85m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
0f2c8df0fee22bbc, retrieved 2026-10-27, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HC85M96
**Texas Instruments** · Logic ICs · SOP-16
CD74HC85M96 from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B3 | input | Most significant bit of 4-bit word B, a comparing input. |
| 2 | (A < B) IN | input | Cascading input for the A less than B result from a preceding stage, used for serial or parallel expansion. |
| 3 | (A = B) IN | input | Cascading input for the A equals B result from a preceding stage, used for serial or parallel expansion. |
| 4 | (A > B) IN | input | Cascading input for the A greater than B result from a preceding stage, used for serial or parallel expansion. |
| 5 | (A > B) OUT | output | Buffered output that goes high when word A is greater than word B. |
| 6 | (A = B) OUT | output | Buffered output that goes high when word A equals word B. |
| 7 | (A < B) OUT | output | Buffered output that goes high when word A is less than word B. |
| 8 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±50 mA. |
| 9 | B0 | input | Least significant bit of 4-bit word B, a comparing input. |
| 10 | A0 | input | Least significant bit of 4-bit word A, a comparing input. |
| 11 | B1 | input | Bit 1 of 4-bit word B, a comparing input. |
| 12 | A1 | input | Bit 1 of 4-bit word A, a comparing input. |
| 13 | A2 | input | Bit 2 of 4-bit word A, a comparing input. |
| 14 | B2 | input | Bit 2 of 4-bit word B, a comparing input. |
| 15 | A3 | input | Most significant bit of 4-bit word A, a comparing input. |
| 16 | VCC | power_in | Supply voltage of 2 V to 6 V for HC types, with a 0.1-µF bypass capacitor recommended close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-16 |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (HC types) | VCC | 2 | | 6 | V | HC types | 4 |
| Input or output voltage | VI, VO | 0 | | | V | Maximum is VCC | 4 |
| Input rise and fall time | | | | 1000 | ns | VCC = 2 V | 4 |
| Input rise and fall time | | | | 500 | ns | VCC = 4.5 V | 4 |
| Input rise and fall time | | | | 400 | ns | VCC = 6 V | 4 |
| Temperature range | TA | -55 | | 125 | °C | | 4 |
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input diode current | IIK | -20 | | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output diode current | IOK | -20 | | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Output source or sink current per output pin | IO | -25 | | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 |
| Continuous current through VCC or GND | ICC | -50 | | 50 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 4 |
| Lead temperature | | | | 300 | °C | Soldering 10 s (SOIC - lead tips only) | 4 |
| Junction-to-ambient thermal resistance | RθJA | | 73 | | °C/W | D (SOIC) 16-pin package | 4 |
| High level input voltage | VIH | 1.5 | | | V | VCC = 2 V | 5 |
| High level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V | 5 |
| High level input voltage | VIH | 4.2 | | | V | VCC = 6 V | 5 |
| Low level input voltage | VIL | | | 0.5 | V | VCC = 2 V | 5 |
| Low level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V | 5 |
| Low level input voltage | VIL | | | 1.8 | V | VCC = 6 V | 5 |
| High level output voltage | VOH | 1.9 | | | V | IOH = -20 μA; VCC = 2 V | 5 |
| High level output voltage | VOH | 4.4 | | | V | IOH = -20 μA; VCC = 4.5 V | 5 |
| High level output voltage | VOH | 5.9 | | | V | IOH = -20 μA; VCC = 6 V | 5 |
| High level output voltage | VOH | 3.98 | | | V | IOH = -4 mA; VCC = 4.5 V; 25°C | 5 |
| High level output voltage | VOH | 5.48 | | | V | IOH = -5.2 mA; VCC = 6 V; 25°C | 5 |
| Low level output voltage | VOL | | | 0.1 | V | IOL = 20 μA; VCC = 2 V | 5 |
| Low level output voltage | VOL | | | 0.26 | V | IOL = 4 mA; VCC = 4.5 V; 25°C | 5 |
| Input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6 V; TA = -55 to 125°C | 5 |
| Supply current | ICC | | 8 | 80 | μA | VI = VCC or GND; VCC = 6 V; 25°C | 5 |
| Supply current | ICC | | | 160 | μA | VI = VCC or GND; VCC = 6 V; TA = -55 to 125°C | 5 |
| Propagation delay An, Bn to (A > B) OUT, (A < B) OUT | tPLH, tPHL | | | 295 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 |
| Propagation delay An, Bn to (A = B) OUT | tPLH, tPHL | | | 265 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 |
| Propagation delay (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT | tPLH, tPHL | | | 210 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 |
| Propagation delay (A > B) IN to (A = B) OUT | tPLH, tPHL | | | 180 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 |
| Propagation delay An, Bn to (A > B) OUT, (A < B) OUT | tPLH, tPHL | | | 50 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 |
| Propagation delay An, Bn to (A = B) OUT | tPLH, tPHL | | | 45 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 |
| Propagation delay (A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT | tPLH, tPHL | | | 36 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 |
| Propagation delay (A > B) IN to (A = B) OUT | tPLH, tPHL | | | 31 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 |
| Output transition times | tTLH, tTHL | | | 110 | ns | Input tr, tf = 6 ns; VCC = 2 V; TA = -55 to 125°C | 6 |
| Output transition times | tTLH, tTHL | | | 19 | ns | Input tr, tf = 6 ns; VCC = 6 V; TA = -55 to 125°C | 6 |
| Input capacitance | CIN | | 10 | | pF | | 6 |
| Power dissipation capacitance | CPD | | 24 | | pF | VCC = 5 V | 6 |
## CAD (KiCad official)
- Symbol: `CD74HC85M96`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd74hc85m96-etched.step` / `cd74hc85m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc85m96.step` / `cd74hc85m96.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc85m96.pdf) (30 pp, sha256 `0f2c8df0fee22bbc`, retrieved 2026-10-27, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hc85m96-datasheet.pdf)