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docs cd74hc73m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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cd74hc73m96-etched.glb cd74hc73m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd74hc73m96-etched.step cd74hc73m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd74hc73m96.glb Publish 0.1.0 · Ray
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package.json cd74hc73m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
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README.md Initial commit: component/cd74hc73m96 · Ray

CD74HC73M96

Texas Instruments · Flip Flops · SOIC-14

CD74HC73M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input for flip-flop 1; the device changes state on the negative-going (high-to-low) transition of this clock pulse, with input hysteresis for improved noise immunity.
2 1R input Active-low asynchronous Reset for flip-flop 1; when low, forces Q to low and Q-bar to high regardless of J, K, or CP.
3 1K input Synchronous K data input for flip-flop 1, sampled on the negative-going edge of 1CP per the truth table.
4 VCC power_in Positive supply voltage; recommended operating range 2V to 6V for HC types or 4.5V to 5.5V for HCT types.
5 2CP input Clock input for flip-flop 2; the device changes state on the negative-going (high-to-low) transition of this clock pulse, with input hysteresis for improved noise immunity.
6 2R input Active-low asynchronous Reset for flip-flop 2; when low, forces Q to low and Q-bar to high regardless of J, K, or CP.
7 2J input Synchronous J data input for flip-flop 2, sampled on the negative-going edge of 2CP per the truth table.
8 2Q output Inverted (complementary) output of flip-flop 2, buffered totem-pole output capable of driving 10 LSTTL loads.
9 2Q output True output of flip-flop 2, buffered totem-pole output capable of driving 10 LSTTL loads.
10 2K input Synchronous K data input for flip-flop 2, sampled on the negative-going edge of 2CP per the truth table.
11 GND power_in Ground reference (0V) for the device.
12 1Q output True output of flip-flop 1, buffered totem-pole output capable of driving 10 LSTTL loads.
13 1Q output Inverted (complementary) output of flip-flop 1, buffered totem-pole output capable of driving 10 LSTTL loads.
14 1J input Synchronous J data input for flip-flop 1, sampled on the negative-going edge of 1CP per the truth table.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD74HC73M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hc73m96-etched.step / cd74hc73m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc73m96.step / cd74hc73m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 c850ead01d9c83eb, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF