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CD74HC7046AM96
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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC7046AM96++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · SOIC-16++CD74HC7046AM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LD | output | Lock Detector Output (active high) gives a HIGH level when the PLL is locked. |+| 2 | PC1OUT | output | Phase Comparator 1 output (Exclusive-OR network) is low-pass filtered to form the VCO control voltage at DEMOUT. |+| 3 | COMPIN | input | Comparator input receives the VCO output, either directly or through a frequency divider, and is compared with SIGIN. |+| 4 | VCOOUT | output | VCO output has a specified duty factor of 50% and can be connected directly to COMPIN or via a frequency divider. |+| 5 | INH | input | Inhibit input: a LOW level enables the VCO, and a HIGH level disables the VCO to minimize standby power consumption. |+| 6 | C1A | passive | Connection A for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range. |+| 7 | C1B | passive | Connection B for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range. |+| 8 | GND | power_in | Ground (0V) reference; the lock detector capacitor is connected between CLD (pin 15) and this pin. |+| 9 | VCOIN | input | VCO input has high input impedance, which simplifies low-pass filter design by not loading the filter. |+| 10 | DEMOUT | output | Demodulator output equals the VCO input voltage; if used, a load resistor RS should be connected from DEMOUT to Gnd, and if unused it should be left open. |+| 11 | R1 | passive | Resistor R1 connection, to Gnd, which together with C1 determines the VCO frequency range. |+| 12 | R2 | passive | Resistor R2 connection, to Gnd, which enables a VCO frequency offset if required. |+| 13 | PC2OUT | tri_state | Phase Comparator 2 three-state output of the positive edge-triggered phase and frequency detector, filtered to form the VCO control voltage. |+| 14 | SIGIN | input | Signal input is self-biased and can be directly coupled to signals within the HC input logic levels, or capacitively coupled for smaller swings. |+| 15 | CLD | passive | Lock detector capacitor input; the capacitor is connected between CLD and Gnd, about 1000pF for 100kHz and 10pF for 10MHz. |+| 16 | VCC | power_in | Positive supply voltage: 3V to 6V for the VCO section and 2V to 6V for the digital section. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC7046AM96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc7046am96-etched.step` / `cd74hc7046am96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc7046am96.step` / `cd74hc7046am96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct7046a) (29 pp, sha256 `e6707ac729144ed7`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc7046am96-datasheet.pdf)
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the lock detector capacitor is connected between CLD (pin 15) and this pin."+ },+ {+ "number": "9",+ "name": "VCOIN",+ "type": "input",+ "description": "VCO input has high input impedance, which simplifies low-pass filter design by not loading the filter."+ },+ {+ "number": "10",+ "name": "DEMOUT",+ "type": "output",+ "description": "Demodulator output equals the VCO input voltage; if used, a load resistor RS should be connected from DEMOUT to Gnd, and if unused it should be left open."+ },+ {+ "number": "11",+ "name": "R1",+ "type": "passive",+ "description": "Resistor R1 connection, to Gnd, which together with C1 determines the VCO frequency range."+ },+ {+ "number": "12",+ "name": "R2",+ "type": "passive",+ "description": "Resistor R2 connection, to Gnd, which enables a VCO frequency offset if required."+ },+ {+ "number": "13",+ "name": "PC2OUT",+ "type": "tri_state",+ "description": "Phase Comparator 2 three-state output of the positive edge-triggered phase and frequency detector, filtered to form the VCO control voltage."+ },+ {+ "number": "14",+ "name": "SIGIN",+ "type": "input",+ "description": "Signal input is self-biased and can be directly coupled to signals within the HC input logic levels, or capacitively coupled for smaller swings."+ },+ {+ "number": "15",+ "name": "CLD",+ "type": "passive",+ "description": "Lock detector capacitor input; the capacitor is connected between CLD and Gnd, about 1000pF for 100kHz and 10pF for 10MHz."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage: 3V to 6V for the VCO section and 2V to 6V for the digital section."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The page 2 TOP VIEW pinout drawing is garbled in the extracted text, so pin positions around the pac; Pin types are KiCad ERC classes inferred from the text. PC2OUT is tri_state because the datasheet de; The datasheet is an extract (8 of 29 pages). The ordering table (page 1) and package addendum (page "+ ],+ "pages_sent": 8,+ "cost_usd": 0.0636,+ "at": "2026-10-08T02:40:50"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct7046a",+ "pages": 29,+ "sha256": "e6707ac729144ed7",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hc7046am96.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hc7046am96-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "77f982d6ae30b4e707be7bcc707af75e3564f079ab0fb06e32aad1aaa1245d0b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}