Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	11d ago
viewers	cd74hc597m: viewers · Ray	11d ago
cd74hc597m-etched.glb	cd74hc597m: factory component page (tier=lcsc) · Ray	11d ago
cd74hc597m-etched.step	cd74hc597m: factory component page (tier=lcsc) · Ray	11d ago
cd74hc597m-hero.glb	cd74hc597m: hero GLB from the etched model (keeps the MPN mark) · Ray	11d ago
cd74hc597m-hero.overlay.json	Publish 0.1.0 · Ray	11d ago
cd74hc597m.glb	Publish 0.1.0 · Ray	11d ago
cd74hc597m.kicad_mod	Publish 0.1.0 · Ray	11d ago
cd74hc597m.kicad_sym	Publish 0.1.0 · Ray	11d ago
cd74hc597m.lbr	Publish 0.1.0 · Ray	11d ago
cd74hc597m.step	Publish 0.1.0 · Ray	11d ago
package.json	Publish 0.1.0 · Ray	11d ago
page.json	Set visibility: public · Ray	11d ago
README.md	Publish 0.1.0 · Ray	11d ago

CD74HC597M

Texas Instruments · Shift Registers · SOIC-16

CD74HC597M from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	input	Parallel data input to storage flip-flop 1, loaded into the input flip-flops on the rising edge of STCP.
2	D2	input	Parallel data input to storage flip-flop 2, loaded into the input flip-flops on the rising edge of STCP.
3	D3	input	Parallel data input to storage flip-flop 3, loaded into the input flip-flops on the rising edge of STCP.
4	D4	input	Parallel data input to storage flip-flop 4, loaded into the input flip-flops on the rising edge of STCP.
5	D5	input	Parallel data input to storage flip-flop 5, loaded into the input flip-flops on the rising edge of STCP.
6	D6	input	Parallel data input to storage flip-flop 6, loaded into the input flip-flops on the rising edge of STCP.
7	D7	input	Parallel data input to storage flip-flop 7, loaded into the input flip-flops on the rising edge of STCP.
8	GND	power_in	Ground reference for the device.
9	Q7	output	Serial output of the 8-bit shift register (Q7 = Q6 of the previous stage, per the shift-register function table).
10	MR	input	Active-low master reset; a low level clears the shift register while PL is high.
11	SHCP	input	Shift register clock; the shift register is clocked on its low-to-high transition when MR and PL are high.
12	STCP	input	Storage register clock; a low-to-high transition loads the Dn parallel data into the input flip-flops.
13	PL	input	Active-low asynchronous parallel load; a low level shifts the stored parallel data into the shift register.
14	DS	input	Serial data input to the shift register, shifted into Q0 on SHCP when PL and MR are high.
15	D0	input	Parallel data input to storage flip-flop 0, loaded into the input flip-flops on the rising edge of STCP.
16	VCC	power_in	Positive supply: 2 V to 6 V for HC types and 4.5 V to 5.5 V for HCT types.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: CD74HC597M
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cd74hc597m-etched.step / cd74hc597m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc597m.step / cd74hc597m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 8a29584772861b6c, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF