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CD74HC597E

Public Made by Adom

by adom

Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icscd74hc597efactory-2.0.0extractor-text

Verified CD74HC597E

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC597E · PDIP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 23-page datasheet
  • ✓distributor: lcsc C2866529, digikey 296-26011-5-ND, mouser 595-CD74HC597E
  • ✓family: DIP-16_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5hhhcnwr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc597e.kicad_sym✓ cd74hc597e.kicad_mod✓ cd74hc597e.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12h ago
viewers cd74hc597e: viewers · Ray 12h ago
cd74hc597e-etched.glb Publish 0.1.0 · Ray 12h ago
cd74hc597e-etched.step cd74hc597e: factory component page (tier=mfr) · Ray 12h ago
cd74hc597e-hero.glb cd74hc597e: hero GLB from the etched model (keeps the MPN mark) · Ray 12h ago
cd74hc597e-hero.overlay.json Publish 0.1.0 · Ray 12h ago
cd74hc597e.glb Publish 0.1.0 · Ray 12h ago
cd74hc597e.kicad_mod Publish 0.1.0 · Ray 12h ago
cd74hc597e.kicad_sym Publish 0.1.0 · Ray 12h ago
cd74hc597e.lbr Publish 0.1.0 · Ray 12h ago
cd74hc597e.step Publish 0.1.0 · Ray 12h ago
package.json Publish 0.1.0 · Ray 12h ago
page.json Set visibility: public · Ray 12h ago
README.md Publish 0.1.0 · Ray 12h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 12h ago

CD74HC597E

Texas Instruments · Shifting Register · PDIP-16

CD74HC597E from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input D1 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
2 D2 input Parallel data input D2 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
3 D3 input Parallel data input D3 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
4 D4 input Parallel data input D4 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
5 D5 input Parallel data input D5 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
6 D6 input Parallel data input D6 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
7 D7 input Parallel data input D7 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
8 GND power_in Ground reference for the device.
9 Q7 output Serial data output from the last stage of the 8-bit shift register (Qn = Qn-1 on each SHCP rising edge).
10 MR input Active-low master reset input; when low (with PL high) it clears the shift register.
11 SHCP input Shift register clock input; the shift register shifts on the low-to-high transition when PL is high and MR is high.
12 STCP input Storage register clock input; a low-to-high transition loads the Dn data into the input flip-flops.
13 PL input Active-low asynchronous parallel load input; when low it shifts the parallel stored data into the shift register.
14 DS input Serial data input to the first shift register stage (Q0), shifted in on the SHCP rising edge.
15 D0 input Parallel data input D0 to the 8-bit input storage flip-flops, which are loaded on the rising edge of STCP.
16 VCC power_in Positive supply voltage; 2 V to 6 V for HC types, as stated in the operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range, VCC (HC types) VCC 2 6 V HC types 3
Temperature Range, TA TA -55 125 °C 3
Input Rise and Fall Time 1000 ns VCC = 2 V 3
Input Rise and Fall Time 500 ns VCC = 4.5 V 3
Input Rise and Fall Time 400 ns VCC = 6 V 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Diode Current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
DC Output Diode Current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
DC Drain Current, per Output IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
DC Output Source or Sink Current per Output Pin IO -25 25 mA VO > -0.5 V or VO < VCC + 0.5 V 3
DC VCC or Ground Current ICC -50 50 mA 3
Maximum Storage Temperature Range -65 150 °C 3
Maximum Junction Temperature 150 °C 3
Maximum Lead Temperature (Soldering 10 s) 300 °C Soldering 10 s 3
High Level Input Voltage VIH 1.5 V VCC = 2 V; -55°C to 125°C 4
Low Level Input Voltage VIL 1.8 V VCC = 6 V; -55°C to 125°C 4
High Level Output Voltage, CMOS Loads VOH 1.9 V VI = VIH or VIL; IO = -0.02 mA; VCC = 2 V; -55°C to 125°C 3
High Level Output Voltage, CMOS Loads VOH 4.4 V VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V; -55°C to 125°C 3
High Level Output Voltage, CMOS Loads VOH 5.9 V VI = VIH or VIL; IO = -0.02 mA; VCC = 6 V; -55°C to 125°C 3
High Level Output Voltage, TTL Loads VOH 3.7 V IO = -4 mA; VCC = 4.5 V; -55°C to 125°C 3
High Level Output Voltage, TTL Loads VOH 5.2 V IO = -5.2 mA; VCC = 6 V; -55°C to 125°C 3
Low Level Output Voltage, CMOS Loads VOL 0.1 V VI = VIH or VIL; IO = 0.02 mA; VCC = 2 V; -55°C to 125°C 3
Low Level Output Voltage, TTL Loads VOL 0.4 V IO = 4 mA; VCC = 4.5 V; -55°C to 125°C 3
Input Leakage Current II -1 1 µA VI = VCC or GND; VCC = 6 V; -55°C to 125°C 3
Quiescent Device Current ICC 160 µA VI = VCC or GND; IO = 0; VCC = 6 V; -55°C to 125°C 3
Propagation Delay SHCP to Q7 tPLH, tPHL 265 ns tr, tf = 6 ns; CL = 50 pF; VCC = 2 V; -55°C to 125°C 5
Propagation Delay SHCP to Q7 tPLH, tPHL 53 ns tr, tf = 6 ns; CL = 50 pF; VCC = 4.5 V; -55°C to 125°C 5
Propagation Delay SHCP to Q7 tPLH, tPHL 45 ns tr, tf = 6 ns; CL = 50 pF; VCC = 6 V; -55°C to 125°C 5
Propagation Delay PL to Q7 tPLH, tPHL 300 ns tr, tf = 6 ns; CL = 50 pF; VCC = 2 V; -55°C to 125°C 5
Propagation Delay PL to Q7 tPLH, tPHL 60 ns tr, tf = 6 ns; CL = 50 pF; VCC = 4.5 V; -55°C to 125°C 5
Propagation Delay PL to Q7 tPLH, tPHL 51 ns tr, tf = 6 ns; CL = 50 pF; VCC = 6 V; -55°C to 125°C 5
Propagation Delay STCP to Q7 tPLH, tPHL 360 ns tr, tf = 6 ns; CL = 50 pF; VCC = 2 V; -55°C to 125°C 5
Propagation Delay STCP to Q7 tPLH, tPHL 72 ns tr, tf = 6 ns; CL = 50 pF; VCC = 4.5 V; -55°C to 125°C 5
Propagation Delay STCP to Q7 tPLH, tPHL 61 ns tr, tf = 6 ns; CL = 50 pF; VCC = 6 V; -55°C to 125°C 5
Propagation Delay MR to Q7 tPLH, tPHL 265 ns tr, tf = 6 ns; CL = 50 pF; VCC = 2 V; -55°C to 125°C 5
Propagation Delay MR to Q7 tPLH, tPHL 53 ns tr, tf = 6 ns; CL = 50 pF; VCC = 4.5 V; -55°C to 125°C 5
Propagation Delay MR to Q7 tPLH, tPHL 45 ns tr, tf = 6 ns; CL = 50 pF; VCC = 6 V; -55°C to 125°C 5
Output Transition Time tTLH, tTHL 110 ns tr, tf = 6 ns; CL = 50 pF; VCC = 2 V; -55°C to 125°C 5
Output Transition Time tTLH, tTHL 22 ns tr, tf = 6 ns; CL = 50 pF; VCC = 4.5 V; -55°C to 125°C 5
Output Transition Time tTLH, tTHL 19 ns tr, tf = 6 ns; CL = 50 pF; VCC = 6 V; -55°C to 125°C 5
Input Capacitance CI 10 pF CL = 50 pF; -55°C to 125°C 5
SHCP Frequency fMAX 20 MHz VCC = 4.5 V; -55°C to 125°C 4
SHCP Pulse Width tW 24 ns VCC = 4.5 V; -55°C to 125°C 5
STCP Pulse Width tW 18 ns VCC = 4.5 V; -55°C to 125°C 5
MR Pulse Width tW 24 ns VCC = 4.5 V; -55°C to 125°C 5
PL Pulse Width tW 21 ns VCC = 4.5 V; -55°C to 125°C 5
STCP to SHCP Setup Time tSU 30 ns VCC = 4.5 V; -55°C to 125°C 5
DS to SHCP Setup Time / Dn to STCP Setup Time tSU 15 ns VCC = 4.5 V; -55°C to 125°C 5
STCP to SHCP Hold Time tH 0 ns VCC = 4.5 V; -55°C to 125°C 5
DS to SHCP Hold Time / Dn to STCP Hold Time tH 3 ns VCC = 4.5 V; -55°C to 125°C 5
MR to SHCP Removal Time tREM 3 ns VCC = 4.5 V; -55°C to 125°C 5
Thermal Resistance, PDIP (E) Package θJA 67 °C/W Typical, per JESD 51-7; E (PDIP) package 3

CAD (KiCad official)

  • Symbol: CD74HC597E
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc597e-etched.step / cd74hc597e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc597e.step / cd74hc597e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 e5266044e80e9078, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF