component
CD74HC595M96
Public Made by Adomby adom
Texas Instruments Shifting Register, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
f860d8b
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{
"schema": "adom.pads/1",
"slug": "cd74hc595m96",
"footprint": "SOIC-16_3.9x9.9mm_P1.27mm",
"generated_from": {
"footprint": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
"pins": "page.json:component.pins",
"overrides": null
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-4.445
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c"
},
"pad_count": 16,
"symbol_pins": [
"1",
"10",
"11",
"12",
"13",
"14",
"15",
"16",
"2",
"3",
"4",
"5",
"6",
"7",
"8",
"9"
],
"paste_apertures": 0,
"issues": [],
"pads": [
{
"pad": "1",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-4.445
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "1",
"name": "QB",
"type": "tri_state",
"description": "3-state parallel output bit B of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": true,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "2",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-3.175
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "2",
"name": "QC",
"type": "tri_state",
"description": "3-state parallel output bit C of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "3",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "3",
"name": "QD",
"type": "tri_state",
"description": "3-state parallel output bit D of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "4",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "4",
"name": "QE",
"type": "tri_state",
"description": "3-state parallel output bit E of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "5",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "5",
"name": "QF",
"type": "tri_state",
"description": "3-state parallel output bit F of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "6",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "6",
"name": "QG",
"type": "tri_state",
"description": "3-state parallel output bit G of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "7",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
3.175
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "7",
"name": "QH",
"type": "tri_state",
"description": "3-state parallel output bit H (MSB) of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "8",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
4.445
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0 V) for the device.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "9",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
4.445
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "9",
"name": "QH'",
"type": "output",
"description": "Serial data output from the last stage of the shift register (not 3-state). Used to cascade multiple CD74HC595 devices by connecting QH' to the SER input of the next stage.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "10",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
3.175
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "10",
"name": "SRCLR",
"type": "input",
"description": "Active-low direct overriding shift-register clear. When held low, the shift register is asynchronously cleared; the storage register is unaffected.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "11",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "11",
"name": "SRCLK",
"type": "input",
"description": "Shift-register clock input. On each positive edge, serial data on SER is shifted into the 8-bit shift register.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "12",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "12",
"name": "RCLK",
"type": "input",
"description": "Storage-register (latch) clock input. On each positive edge, the contents of the shift register are transferred to the 8-bit storage register and appear at QA-QH.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "13",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "13",
"name": "OE",
"type": "input",
"description": "Active-low output-enable for the QA-QH 3-state outputs. When high, QA-QH are placed in the high-impedance state; when low, storage-register data drives the outputs. Does not affect QH'.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "14",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "14",
"name": "SER",
"type": "input",
"description": "Serial data input to the first stage of the shift register. Sampled on the positive edge of SRCLK.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "15",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-3.175
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "15",
"name": "QA",
"type": "tri_state",
"description": "3-state parallel output bit A (LSB) of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "16",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-4.445
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply voltage input. Recommended operating range 2 V to 6 V (5 V nominal); absolute maximum 7 V.",
"is_pin1": false,
"source": {
"geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
}
]
}