CD74HC595DWR

{
  "slug": "cd74hc595dwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Shift Registers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd74hc595dwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd74hc595dwr.kicad_sym",
    "cd74hc595dwr.kicad_mod",
    "cd74hc595dwr.glb",
    "cd74hc595dwr.step",
    "cd74hc595dwr.lbr",
    "docs/hero.png",
    "docs/cd74hc595dwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd74hc595dwr-hero.glb",
    "cd74hc595dwr-hero.overlay.json"
  ],
  "component": {
    "mpn": "CD74HC595DWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16-300mil",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc595",
    "parts": {
      "symbol": "cd74hc595dwr.kicad_sym",
      "footprint": "cd74hc595dwr.kicad_mod",
      "model_3d": "cd74hc595dwr-hero.glb",
      "model_3d_plain": "cd74hc595dwr.glb",
      "model_3d_step": "cd74hc595dwr-etched.step",
      "model_3d_step_plain": "cd74hc595dwr.step",
      "lbr": "cd74hc595dwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2871241",
      "digikey": "296-18401-2-ND",
      "mouser": "595-CD74HC595DWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T03:17:16Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-18401-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-CD74HC595DWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel 3-state output bit B of the storage register; high-impedance when OE is high."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel 3-state output bit C of the storage register; high-impedance when OE is high."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel 3-state output bit D of the storage register; high-impedance when OE is high."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel 3-state output bit E of the storage register; high-impedance when OE is high."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel 3-state output bit F of the storage register; high-impedance when OE is high."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel 3-state output bit G of the storage register; high-impedance when OE is high."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel 3-state output bit H of the storage register; high-impedance when OE is high."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "9",
        "name": "QH'",
        "type": "output",
        "description": "Serial data output from the last shift register stage, used for cascading devices; it is not 3-state."
      },
      {
        "number": "10",
        "name": "SRCLR",
        "type": "input",
        "description": "Active-low shift register clear; a low level clears the shift register (asynchronous, direct overriding clear)."
      },
      {
        "number": "11",
        "name": "SRCLK",
        "type": "input",
        "description": "Shift register clock, positive-edge triggered; SER is shifted in on the rising edge."
      },
      {
        "number": "12",
        "name": "RCLK",
        "type": "input",
        "description": "Storage register (output latch) clock, positive-edge triggered; shift register data is transferred to the outputs on the rising edge."
      },
      {
        "number": "13",
        "name": "OE",
        "type": "input",
        "description": "Output enable, active low: when high, outputs QA-QH are forced to the high-impedance state."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the 8-bit shift register; sampled on the rising edge of SRCLK, with thold of 0 ns after SRCLK at 2-6 V."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel 3-state output bit A of the storage register; high-impedance when OE is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 2 V to 6 V recommended (absolute maximum 7 V); bypass with a 0.1 µF capacitor close to the pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-number to name mapping was reconstructed from scrambled text extraction of the pin diagram (; Output pin numbers QA–QH were taken from the scrambled pin diagram text; the standard sequence (QB=1; Datasheet gives no per-pin electrical limits beyond the device-level recommended operating condition"
        ],
        "pages_sent": 33,
        "cost_usd": 0.0941,
        "at": "2026-10-08T03:17:00"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hc595",
        "pages": 33,
        "sha256": "9ed505a61666567b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd74hc595dwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd74hc595dwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8eaae4f6d30d89103b7bf6b12839195bb21ed3d7cdf1ba7dac6a173fb00942a5",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}