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CD74HC573E

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by adom

Texas Instruments Latches, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

CD74HC573E

Texas Instruments · Latches · PDIP-20

CD74HC573E from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input that places the eight Q outputs in a normal logic state when low or in the high-impedance state when high, without affecting the latches' internal operation.
2 1D input Latch 1 data input; Q follows D while LE is high and holds the level when LE goes low.
3 2D input Latch 2 data input; Q follows D while LE is high and holds the level when LE goes low.
4 3D input Latch 3 data input; Q follows D while LE is high and holds the level when LE goes low.
5 4D input Latch 4 data input; Q follows D while LE is high and holds the level when LE goes low.
6 5D input Latch 5 data input; Q follows D while LE is high and holds the level when LE goes low.
7 6D input Latch 6 data input; Q follows D while LE is high and holds the level when LE goes low.
8 7D input Latch 7 data input; Q follows D while LE is high and holds the level when LE goes low.
9 8D input Latch 8 data input; Q follows D while LE is high and holds the level when LE goes low.
10 GND power_in Ground.
11 LE input Latch-enable input; Q outputs follow the D inputs when high and are latched at the D levels when low.
12 8Q tri_state Latch 8 three-state output; high-impedance when OE is high.
13 7Q tri_state Latch 7 three-state output; high-impedance when OE is high.
14 6Q tri_state Latch 6 three-state output; high-impedance when OE is high.
15 5Q tri_state Latch 5 three-state output; high-impedance when OE is high.
16 4Q tri_state Latch 4 three-state output; high-impedance when OE is high.
17 3Q tri_state Latch 3 three-state output; high-impedance when OE is high.
18 2Q tri_state Latch 2 three-state output; high-impedance when OE is high.
19 1Q tri_state Latch 1 three-state output; high-impedance when OE is high.
20 VCC power_in Supply voltage, 2 V to 6 V operation, with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output drain current per output IO -35 35 mA VO = 0 to VCC 4
Continuous output source or sink current per output IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature (printed as Storage temperature) TJ 150 ℃ 4
Storage temperature range Tstg -65 150 ℃ 4
Supply voltage VCC 2 6 V TA = -55°C to 125°C 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage (max printed as VCC) VI 0 V 4
Output voltage (max printed as VCC) VO 0 V 4
Input transition (rise and fall) time tt 1000 ns VCC = 2 V 4
Input transition (rise and fall) time tt 500 ns VCC = 4.5 V 4
Input transition (rise and fall) time tt 400 ns VCC = 6 V 4
Junction-to-ambient thermal resistance RθJA 84.6 °C/W PDIP (N), 20 pins 4
Junction-to-case (top) thermal resistance RθJC (top) 72.5 °C/W PDIP (N), 20 pins 4
Junction-to-board thermal resistance RθJB 65.3 °C/W PDIP (N), 20 pins 4
High-level output voltage VOH 1.9 V VI = VIH or VIL; IOH = -20 μA; VCC = 2 V 5
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = -20 μA; VCC = 4.5 V 5
High-level output voltage VOH 5.9 V VI = VIH or VIL; IOH = -20 μA; VCC = 6 V 5
High-level output voltage VOH 3.7 V VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V 5
High-level output voltage VOH 5.2 V VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 20 μA; VCC = 2 V 5
Low-level output voltage VOL 0.4 V VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V 5
Input leakage current II -1 1 μA VI = VCC or 0; VCC = 6 V 5
Off-state (high-impedance) output current IOZ -10 10 μA VO = VCC or 0; VCC = 6 V 5
Quiescent supply current ICC 160 μA VI = VCC or 0, IO = 0; VCC = 6 V 5
Pulse duration, LE high tw 120 ns VCC = 2 V; TA = -55°C to 125°C 5
Pulse duration, LE high tw 24 ns VCC = 4.5 V; TA = -55°C to 125°C 5
Pulse duration, LE high tw 20 ns VCC = 6 V; TA = -55°C to 125°C 5
Setup time, data before LE↓ tsu 75 ns VCC = 2 V; TA = -55°C to 125°C 5
Setup time, data before LE↓ tsu 15 ns VCC = 4.5 V; TA = -55°C to 125°C 5
Setup time, data before LE↓ tsu 13 ns VCC = 6 V; TA = -55°C to 125°C 5
Hold time, data after LE↓ th 60 ns VCC = 2 V; TA = -55°C to 125°C 5
Hold time, data after LE↓ th 12 ns VCC = 4.5 V; TA = -55°C to 125°C 5
Hold time, data after LE↓ th 10 ns VCC = 6 V; TA = -55°C to 125°C 5
Propagation delay, D to Q tpd 265 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Propagation delay, D to Q tpd 53 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Propagation delay, D to Q tpd 45 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6
Propagation delay, LE to Q tpd 265 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Propagation delay, LE to Q tpd 53 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Propagation delay, LE to Q tpd 45 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6
Output enable time, OE to Q ten 225 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Output enable time, OE to Q ten 45 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Output enable time, OE to Q ten 38 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6
Output disable time, OE to Q tdis 225 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Output disable time, OE to Q tdis 45 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Output disable time, OE to Q tdis 38 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6
Output transition time, Q tt 90 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Output transition time, Q tt 18 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Output transition time, Q tt 15 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6

CAD (KiCad official)

  • Symbol: CD74HC573E
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: cd74hc573e-etched.step / cd74hc573e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc573e.step / cd74hc573e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 15e5cd2cfa3bdbe5, retrieved 2026-10-16, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF