component
CD74HC564M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownCD74HC564M96
Texas Instruments · Flip Flops · SOIC-20-300mil
CD74HC564M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | /OE | input | Active-low three-state output enable; when HIGH all /Q outputs enter high-impedance state regardless of clock or data inputs. |
| 2 | D0 | input | Data input 0; latched inverted to /Q0 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 3 | D1 | input | Data input 1; latched inverted to /Q1 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 4 | D2 | input | Data input 2; latched inverted to /Q2 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 5 | D3 | input | Data input 3; latched inverted to /Q3 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 6 | D4 | input | Data input 4; latched inverted to /Q4 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 7 | D5 | input | Data input 5; latched inverted to /Q5 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 8 | D6 | input | Data input 6; latched inverted to /Q6 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 9 | D7 | input | Data input 7; latched inverted to /Q7 on the positive-going edge of CP; setup time 12 ns min at VCC = 4.5 V. |
| 10 | GND | power_in | Ground supply reference (0 V); continuous current ±50 mA max. |
| 11 | CP | input | Clock input; data is inverted and transferred to /Q outputs on the positive-going transition; fMAX = 30 MHz typ at VCC = 4.5 V, pulse width 16 ns min at VCC = 4.5 V. |
| 12 | /Q7 | tri_state | Inverted three-state output 7; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 13 | /Q6 | tri_state | Inverted three-state output 6; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 14 | /Q5 | tri_state | Inverted three-state output 5; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 15 | /Q4 | tri_state | Inverted three-state output 4; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 16 | /Q3 | tri_state | Inverted three-state output 3; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 17 | /Q2 | tri_state | Inverted three-state output 2; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 18 | /Q1 | tri_state | Inverted three-state output 1; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 19 | /Q0 | tri_state | Inverted three-state output 0; VOH = 3.98 V min (IOH = −6 mA, VCC = 4.5 V), VOL = 0.26 V max (IOL = 6 mA, VCC = 4.5 V); high-impedance when /OE is HIGH. |
| 20 | VCC | power_in | Positive supply; 2 V to 6 V for HC type; 4.5 V to 5.5 V for HCT type; decouple with 0.1 µF ceramic capacitor as close to pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
CD74HC564M96 - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
cd74hc564m96-etched.step/cd74hc564m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc564m96.step/cd74hc564m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
193165d7e9c18d0c, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).