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CD74HC541PWR

Public Made by Adom

by adom

Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cd74hc541pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hc541pwr: viewers · Ray
cd74hc541pwr-etched.fit.json cd74hc541pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc541pwr-etched.glb cd74hc541pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc541pwr-etched.step cd74hc541pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc541pwr.glb Publish 0.1.0 · Ray
cd74hc541pwr.kicad_mod Publish 0.1.0 · Ray
cd74hc541pwr.kicad_sym Publish 0.1.0 · Ray
cd74hc541pwr.lbr Publish 0.1.0 · Ray
cd74hc541pwr.step Publish 0.1.0 · Ray
package.json cd74hc541pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cd74hc541pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cd74hc541pwr · Ray

CD74HC541PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

CD74HC541PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low Output Enable 1; when either OE1 or OE2 is HIGH the Y outputs go to the high-impedance state, and both must be LOW for data to appear at the outputs.
2 A0 input Buffered noninverting data input 0 that is passed to output Y0 when both output enables are LOW.
3 A1 input Buffered noninverting data input 1 that is passed to output Y1 when both output enables are LOW.
4 A2 input Buffered noninverting data input 2 that is passed to output Y2 when both output enables are LOW.
5 A3 input Buffered noninverting data input 3 that is passed to output Y3 when both output enables are LOW.
6 A4 input Buffered noninverting data input 4 that is passed to output Y4 when both output enables are LOW.
7 A5 input Buffered noninverting data input 5 that is passed to output Y5 when both output enables are LOW.
8 A6 input Buffered noninverting data input 6 that is passed to output Y6 when both output enables are LOW.
9 A7 input Buffered noninverting data input 7 that is passed to output Y7 when both output enables are LOW.
10 GND power_in Ground reference (0 V) supply pin for the device.
11 Y7 tri_state Three-state noninverting buffered output for A7, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
12 Y6 tri_state Three-state noninverting buffered output for A6, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
13 Y5 tri_state Three-state noninverting buffered output for A5, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
14 Y4 tri_state Three-state noninverting buffered output for A4, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
15 Y3 tri_state Three-state noninverting buffered output for A3, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
16 Y2 tri_state Three-state noninverting buffered output for A2, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
17 Y1 tri_state Three-state noninverting buffered output for A1, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
18 Y0 tri_state Three-state noninverting buffered output for A0, capable of driving 15 LSTTL loads; goes high-impedance when OE1 or OE2 is HIGH.
19 OE2 input Active-low Output Enable 2; when either OE1 or OE2 is HIGH the Y outputs go to the high-impedance state, and both must be LOW for data to appear at the outputs.
20 VCC power_in Positive supply voltage pin; recommended operating range is 2 V to 6 V for HC types (4.5 V to 5.5 V for HCT types).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74HC541PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: cd74hc541pwr-etched.step / cd74hc541pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc541pwr.step / cd74hc541pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 51030bc4f84d8bfd, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF