component

CD74HC4538PWR

Public Made by Adom

by adom

Texas Instruments Monostable Multivibrators, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hc4538pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd74hc4538pwr / README.md
History Download
Ray Publish 0.1.0 25d4867 6d ago

CD74HC4538PWR

Texas Instruments · Monostable Multivibrators · TSSOP-16

CD74HC4538PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CX passive External timing capacitor CX for monostable 1; CX minimum is 0pF, and a protection diode or 51Ω series resistor is required when CX is 0.5µF or more.
2 1RXCX passive Common RX/CX timing node for monostable 1; RX minimum is 5kΩ, and the current into this pin must not exceed 30mA.
3 1R input Reset input for monostable 1, which resets the output independently of RX and CX.
4 1A input Leading-edge trigger input for monostable 1 with Schmitt-trigger action; an unused A input must be tied to GND.
5 1B input Trailing-edge trigger input for monostable 1 with Schmitt-trigger action; an unused B input must be tied to VCC.
6 1Q output Buffered output of monostable 1, giving the timed output pulse width set by RX and CX.
7 ~{1Q} output Buffered complementary output of monostable 1.
8 GND power_in Ground reference; all voltages are referenced to ground.
9 ~{2Q} output Buffered complementary output of monostable 2.
10 2Q output Buffered output of monostable 2, giving the timed output pulse width set by RX and CX.
11 2B input Trailing-edge trigger input for monostable 2 with Schmitt-trigger action; an unused B input must be tied to VCC.
12 2A input Leading-edge trigger input for monostable 2 with Schmitt-trigger action; an unused A input must be tied to GND.
13 2R input Reset input for monostable 2, which resets the output independently of RX and CX.
14 2RXCX passive Common RX/CX timing node for monostable 2; RX minimum is 5kΩ, and the current into this pin must not exceed 30mA.
15 2CX passive External timing capacitor CX for monostable 2; CX minimum is 0pF, and a protection diode or 51Ω series resistor is required when CX is 0.5µF or more.
16 VCC power_in Supply voltage: 2V to 6V for HC types and 4.5V to 5.5V for HCT types.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range, HC types VCC 2 6 V HC types 4
Temperature range TA -55 125 °C 4
External timing resistor RX 5 kΩ Note 4 4
External timing capacitor CX 0 Note 4 (Min) 4
Input rise and fall time, reset input tr, tf 1000 ns VCC=2V 4
Input rise and fall time, reset input tr, tf 500 ns VCC=4.5V 4
Input rise and fall time, reset input tr, tf 400 ns VCC=6V 4
DC supply voltage VCC -0.5 7 V 4
DC input diode current IIK -20 20 mA VI < -0.5V or VI > VCC + 0.5V 4
DC output diode current IOK -20 20 mA VO < -0.5V or VO > VCC + 0.5V 4
DC output source or sink current per output pin IO -25 25 mA VO > -0.5V or VO < VCC + 0.5V 4
DC VCC or ground current ICC -50 50 mA 4
Maximum junction temperature 150 °C 4
Maximum storage temperature range -65 150 °C 4
Maximum lead temperature 300 °C Soldering 10s (SOIC lead tips only) 4
Package thermal impedance, PW (TSSOP) θJA 108 °C/W Note 5, JESD 51-7 4
High level input voltage VIH 1.5 V VCC=2V, -55 to 125°C 4
High level input voltage VIH 3.15 V VCC=4.5V, -55 to 125°C 4
High level input voltage VIH 4.2 V VCC=6V, -55 to 125°C 4
Low level input voltage VIL 0.5 V VCC=2V, -55 to 125°C 4
Low level input voltage VIL 1.35 V VCC=4.5V, -55 to 125°C 4
Low level input voltage VIL 1.8 V VCC=6V, -55 to 125°C 4
High level output voltage, CMOS loads VOH 1.9 V VI=VIH or VIL, IO=-0.02mA, VCC=2V, -55 to 125°C 4
High level output voltage, CMOS loads VOH 4.4 V VI=VIH or VIL, IO=-0.02mA, VCC=4.5V, -55 to 125°C 4
High level output voltage, CMOS loads VOH 5.9 V VI=VIH or VIL, IO=-0.02mA, VCC=6V, -55 to 125°C 4
High level output voltage, TTL loads VOH 3.7 V VI=VIH or VIL, IO=-4mA, VCC=4.5V, -55 to 125°C 4
High level output voltage, TTL loads VOH 5.2 V VI=VIH or VIL, IO=-5.2mA, VCC=6V, -55 to 125°C 4
Low level output voltage, CMOS loads VOL 0.1 V VI=VIH or VIL, IO=0.02mA, VCC=2V, -55 to 125°C 5
Low level output voltage, TTL loads VOL 0.4 V VI=VIH or VIL, IO=4mA, VCC=4.5V, -55 to 125°C 5
Input leakage current A, B, R II -1 1 µA VI=VCC or GND, VCC=6V, -55 to 125°C 5
Input leakage current RXCX II -0.5 0.5 µA VI=VCC or GND, VCC=6V, -55 to 125°C, Note 6 5
Quiescent device current ICC 160 µA VI=VCC or GND, IO=0, VCC=6V, -55 to 125°C 5
Active device current, Q high and pins 2, 14 at VCC/4 ICC 1 mA VI=VCC or GND, VCC=6V, -55 to 125°C 5
Input pulse width, A, B tWH, tWL 120 ns VCC=2V, -55 to 125°C 6
Input pulse width, A, B tWH, tWL 24 ns VCC=4.5V, -55 to 125°C 6
Input pulse width, A, B tWH, tWL 20 ns VCC=6V, -55 to 125°C 6
Reset recovery time tREC 5 ns VCC=2V, -55 to 125°C 6
Propagation delay tPLH, A, B to Q tPLH 375 ns CL=50pF, VCC=2V, -55 to 125°C 7
Propagation delay tPLH, A, B to Q tPLH 75 ns CL=50pF, VCC=4.5V, -55 to 125°C 7
Propagation delay tPLH, A, B to Q tPLH 64 ns CL=50pF, VCC=6V, -55 to 125°C 7
Propagation delay tPHL, A, B to Q tPHL 375 ns CL=50pF, VCC=2V, -55 to 125°C 7
Propagation delay tPHL, A, B to Q tPHL 75 ns CL=50pF, VCC=4.5V, -55 to 125°C 7
Propagation delay tPHL, A, B to Q tPHL 64 ns CL=50pF, VCC=6V, -55 to 125°C 7
Propagation delay tPHL, R to Q tPHL 375 ns CL=50pF, VCC=2V, -55 to 125°C 7
Propagation delay tPHL, R to Q tPHL 75 ns CL=50pF, VCC=4.5V, -55 to 125°C 7
Propagation delay tPHL, R to Q tPHL 64 ns CL=50pF, VCC=6V, -55 to 125°C 7
Propagation delay tPLH, R to Q tPLH 375 ns CL=50pF, VCC=2V, -55 to 125°C 7
Propagation delay tPLH, R to Q tPLH 75 ns CL=50pF, VCC=4.5V, -55 to 125°C 7
Propagation delay tPLH, R to Q tPLH 64 ns CL=50pF, VCC=6V, -55 to 125°C 7
Output transition time tTLH, tTHL 110 ns CL=50pF, VCC=2V, -55 to 125°C 7
Output transition time tTLH, tTHL 22 ns CL=50pF, VCC=4.5V, -55 to 125°C 7
Output transition time tTLH, tTHL 19 ns CL=50pF, VCC=6V, -55 to 125°C 7
Output pulse width τ 0.605 0.819 ms RX=10kΩ, CX=0.1µF, CL=50pF, VCC=3V, -55 to 125°C 7
Output pulse width τ 0.595 0.805 ms RX=10kΩ, CX=0.1µF, CL=50pF, VCC=5V, -55 to 125°C 7
Output pulse width match, same package -1 1 % 7
Input capacitance CI 10 pF CL=50pF, -55 to 125°C 7

CAD (KiCad official)

  • Symbol: CD74HC4538PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc4538pwr-etched.step / cd74hc4538pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4538pwr.step / cd74hc4538pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 f6de650fa01c440e, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF