component
CD74HC4538NSR
Public Made by Adomby adom
Texas Instruments Monostable Multivibrators, SO-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HC4538NSR
Texas Instruments · Monostable Multivibrators · SO-16-208mil
CD74HC4538NSR from Texas Instruments, in a SO-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CX | passive | External timing capacitor connection for monostable 1; if CX is 0.5µF or more, a protection diode or 51Ω series resistor is recommended against power-down discharge into pin 2. |
| 2 | 1RXCX | passive | Timing resistor/capacitor node for monostable 1, where RMIN is 5kΩ, maximum current into the pin must be 30mA, and τ = 0.7·RX·CX. |
| 3 | 1R | input | Active-low reset for monostable 1, where a low level forces Q low and Q̄ high and unused resets must be terminated. |
| 4 | 1A | input | Leading-edge trigger input for monostable 1 with Schmitt trigger action, and an unused A input must be tied to GND. |
| 5 | 1B | input | Trailing-edge trigger input for monostable 1 with Schmitt trigger action, and an unused B input must be tied to VCC. |
| 6 | 1Q | output | Buffered true output of monostable 1 (standard outputs rated for 10 LSTTL loads over temperature). |
| 7 | 1Q̄ | output | Buffered complementary output of monostable 1 (standard outputs rated for 10 LSTTL loads over temperature). |
| 8 | GND | power_in | Ground reference; all voltages are referenced to this pin. |
| 9 | 2Q̄ | output | Buffered complementary output of monostable 2 (standard outputs rated for 10 LSTTL loads over temperature). |
| 10 | 2Q | output | Buffered true output of monostable 2 (standard outputs rated for 10 LSTTL loads over temperature). |
| 11 | 2B | input | Trailing-edge trigger input for monostable 2 with Schmitt trigger action, and an unused B input must be tied to VCC. |
| 12 | 2A | input | Leading-edge trigger input for monostable 2 with Schmitt trigger action, and an unused A input must be tied to GND. |
| 13 | 2R | input | Active-low reset for monostable 2, where a low level forces Q low and Q̄ high and unused resets must be terminated. |
| 14 | 2RXCX | passive | Timing resistor/capacitor node for monostable 2, where RMIN is 5kΩ, maximum current into the pin must be 30mA, and τ = 0.7·RX·CX. |
| 15 | 2CX | passive | External timing capacitor connection for monostable 2; if CX is 0.5µF or more, a protection diode or 51Ω series resistor is recommended against power-down discharge into pin 14. |
| 16 | VCC | power_in | Supply voltage: 2V to 6V for HC types and 4.5V to 5.5V for HCT types. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16-208mil |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (HC types) | VCC | 2 | 6 | V | HC types | 4 | |
| Operating temperature range | TA | -55 | 125 | °C | 4 | ||
| Input rise and fall time, reset input | tr, tf | 1000 | ns | VCC = 2 V | 4 | ||
| Input rise and fall time, reset input | tr, tf | 500 | ns | VCC = 4.5 V | 4 | ||
| Input rise and fall time, reset input | tr, tf | 400 | ns | VCC = 6 V | 4 | ||
| External timing resistor | RX | 5 | kΩ | Note 4 | 4 | ||
| DC supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| DC input diode current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| DC output diode current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| DC output source or sink current per output pin | IO | -25 | 25 | mA | VO > -0.5 V or VO < VCC + 0.5 V (as printed) | 4 | |
| DC VCC or ground current | ICC | -50 | 50 | mA | 4 | ||
| Maximum junction temperature | 150 | °C | 4 | ||||
| Maximum storage temperature range | -65 | 150 | °C | 4 | |||
| Package thermal impedance, NS (SOP) package | θJA | 64 | °C/W | NS (SOP) package; JESD 51-7 | 4 | ||
| High level input voltage | VIH | 1.5 | V | VCC = 2 V; -55°C to 125°C | 4 | ||
| High level input voltage | VIH | 3.15 | V | VCC = 4.5 V; -55°C to 125°C | 4 | ||
| High level input voltage | VIH | 4.2 | V | VCC = 6 V; -55°C to 125°C | 4 | ||
| Low level input voltage | VIL | 0.5 | V | VCC = 2 V; -55°C to 125°C | 4 | ||
| Low level input voltage | VIL | 1.35 | V | VCC = 4.5 V; -55°C to 125°C | 4 | ||
| Low level input voltage | VIL | 1.8 | V | VCC = 6 V; -55°C to 125°C | 4 | ||
| High level output voltage, CMOS loads | VOH | 1.9 | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 2 V; -55°C to 125°C | 4 | ||
| High level output voltage, CMOS loads | VOH | 4.4 | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V; -55°C to 125°C | 4 | ||
| High level output voltage, CMOS loads | VOH | 5.9 | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 6 V; -55°C to 125°C | 4 | ||
| High level output voltage, TTL loads | VOH | 3.7 | V | VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V; -55°C to 125°C | 4 | ||
| High level output voltage, TTL loads | VOH | 5.2 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6 V; -55°C to 125°C | 4 | ||
| Low level output voltage, CMOS loads | VOL | 0.1 | V | VI = VIH or VIL; IO = 0.02 mA; VCC = 2 V; -55°C to 125°C | 5 | ||
| Low level output voltage, TTL loads | VOL | 0.4 | V | VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; -55°C to 125°C | 5 | ||
| Input leakage current A, B, R | II | -1 | 1 | µA | VI = VCC or GND; VCC = 6 V; -55°C to 125°C | 5 | |
| Input leakage current RXCX | II | -0.5 | 0.5 | µA | VCC = 6 V; -55°C to 125°C; Note 6 | 5 | |
| Quiescent device current | ICC | 160 | µA | VI = VCC or GND; IO = 0; VCC = 6 V; -55°C to 125°C | 5 | ||
| Active device current | ICC | 1 | mA | Q = High & pins 2, 14 at VCC/4; VI = VCC or GND; IO = 0; VCC = 6 V; -55°C to 125°C | 5 | ||
| Input pulse width, A or B | tWH, tWL | 120 | ns | VCC = 2 V; -55°C to 125°C | 6 | ||
| Input pulse width, A or B | tWH, tWL | 24 | ns | VCC = 4.5 V; -55°C to 125°C | 6 | ||
| Input pulse width, A or B | tWH, tWL | 20 | ns | VCC = 6 V; -55°C to 125°C | 6 | ||
| Input pulse width, R | tWL | 120 | ns | VCC = 2 V; -55°C to 125°C | 6 | ||
| Input pulse width, R | tWL | 24 | ns | VCC = 4.5 V; -55°C to 125°C | 6 | ||
| Input pulse width, R | tWL | 20 | ns | VCC = 6 V; -55°C to 125°C | 6 | ||
| Reset recovery time | tREC | 5 | ns | VCC = 2 V; -55°C to 125°C | 6 | ||
| Propagation delay A, B to Q | tPLH | 375 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 | ||
| Propagation delay A, B to Q | tPLH | 75 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 | ||
| Propagation delay A, B to Q | tPLH | 64 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 | ||
| Propagation delay R to Q | tPHL | 375 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 | ||
| Propagation delay R to Q | tPHL | 75 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 | ||
| Propagation delay R to Q | tPHL | 64 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 | ||
| Output transition time | tTLH, tTHL | 110 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 | ||
| Output transition time | tTLH, tTHL | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 | ||
| Output transition time | tTLH, tTHL | 19 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 | ||
| Output pulse width | τ | 0.595 | 0.805 | ms | VCC = 5 V; RX = 10 kΩ, CX = 0.1 µF; CL = 50 pF; -55°C to 125°C | 7 | |
| Output pulse width match | -1 | 1 | % | Same package | 7 |
CAD (KiCad official)
- Symbol:
CD74HC4538NSR - Footprint:
Adom_Gen:Texas_Instruments_CD74 - 3D model: SO-16-208mil (KiCad packages3D, STEP)
- 3D model files:
cd74hc4538nsr-etched.step/cd74hc4538nsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc4538nsr.step/cd74hc4538nsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
bf04c5a1ae827107, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HC4538NSR
**Texas Instruments** · Monostable Multivibrators · SO-16-208mil
CD74HC4538NSR from Texas Instruments, in a SO-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CX | passive | External timing capacitor connection for monostable 1; if CX is 0.5µF or more, a protection diode or 51Ω series resistor is recommended against power-down discharge into pin 2. |
| 2 | 1RXCX | passive | Timing resistor/capacitor node for monostable 1, where RMIN is 5kΩ, maximum current into the pin must be 30mA, and τ = 0.7·RX·CX. |
| 3 | 1R | input | Active-low reset for monostable 1, where a low level forces Q low and Q̄ high and unused resets must be terminated. |
| 4 | 1A | input | Leading-edge trigger input for monostable 1 with Schmitt trigger action, and an unused A input must be tied to GND. |
| 5 | 1B | input | Trailing-edge trigger input for monostable 1 with Schmitt trigger action, and an unused B input must be tied to VCC. |
| 6 | 1Q | output | Buffered true output of monostable 1 (standard outputs rated for 10 LSTTL loads over temperature). |
| 7 | 1Q̄ | output | Buffered complementary output of monostable 1 (standard outputs rated for 10 LSTTL loads over temperature). |
| 8 | GND | power_in | Ground reference; all voltages are referenced to this pin. |
| 9 | 2Q̄ | output | Buffered complementary output of monostable 2 (standard outputs rated for 10 LSTTL loads over temperature). |
| 10 | 2Q | output | Buffered true output of monostable 2 (standard outputs rated for 10 LSTTL loads over temperature). |
| 11 | 2B | input | Trailing-edge trigger input for monostable 2 with Schmitt trigger action, and an unused B input must be tied to VCC. |
| 12 | 2A | input | Leading-edge trigger input for monostable 2 with Schmitt trigger action, and an unused A input must be tied to GND. |
| 13 | 2R | input | Active-low reset for monostable 2, where a low level forces Q low and Q̄ high and unused resets must be terminated. |
| 14 | 2RXCX | passive | Timing resistor/capacitor node for monostable 2, where RMIN is 5kΩ, maximum current into the pin must be 30mA, and τ = 0.7·RX·CX. |
| 15 | 2CX | passive | External timing capacitor connection for monostable 2; if CX is 0.5µF or more, a protection diode or 51Ω series resistor is recommended against power-down discharge into pin 14. |
| 16 | VCC | power_in | Supply voltage: 2V to 6V for HC types and 4.5V to 5.5V for HCT types. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16-208mil |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (HC types) | VCC | 2 | | 6 | V | HC types | 4 |
| Operating temperature range | TA | -55 | | 125 | °C | | 4 |
| Input rise and fall time, reset input | tr, tf | | | 1000 | ns | VCC = 2 V | 4 |
| Input rise and fall time, reset input | tr, tf | | | 500 | ns | VCC = 4.5 V | 4 |
| Input rise and fall time, reset input | tr, tf | | | 400 | ns | VCC = 6 V | 4 |
| External timing resistor | RX | 5 | | | kΩ | Note 4 | 4 |
| DC supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| DC input diode current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| DC output diode current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| DC output source or sink current per output pin | IO | -25 | | 25 | mA | VO > -0.5 V or VO < VCC + 0.5 V (as printed) | 4 |
| DC VCC or ground current | ICC | -50 | | 50 | mA | | 4 |
| Maximum junction temperature | | | | 150 | °C | | 4 |
| Maximum storage temperature range | | -65 | | 150 | °C | | 4 |
| Package thermal impedance, NS (SOP) package | θJA | | 64 | | °C/W | NS (SOP) package; JESD 51-7 | 4 |
| High level input voltage | VIH | 1.5 | | | V | VCC = 2 V; -55°C to 125°C | 4 |
| High level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V; -55°C to 125°C | 4 |
| High level input voltage | VIH | 4.2 | | | V | VCC = 6 V; -55°C to 125°C | 4 |
| Low level input voltage | VIL | | | 0.5 | V | VCC = 2 V; -55°C to 125°C | 4 |
| Low level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V; -55°C to 125°C | 4 |
| Low level input voltage | VIL | | | 1.8 | V | VCC = 6 V; -55°C to 125°C | 4 |
| High level output voltage, CMOS loads | VOH | 1.9 | | | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 2 V; -55°C to 125°C | 4 |
| High level output voltage, CMOS loads | VOH | 4.4 | | | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 4.5 V; -55°C to 125°C | 4 |
| High level output voltage, CMOS loads | VOH | 5.9 | | | V | VI = VIH or VIL; IO = -0.02 mA; VCC = 6 V; -55°C to 125°C | 4 |
| High level output voltage, TTL loads | VOH | 3.7 | | | V | VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V; -55°C to 125°C | 4 |
| High level output voltage, TTL loads | VOH | 5.2 | | | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6 V; -55°C to 125°C | 4 |
| Low level output voltage, CMOS loads | VOL | | | 0.1 | V | VI = VIH or VIL; IO = 0.02 mA; VCC = 2 V; -55°C to 125°C | 5 |
| Low level output voltage, TTL loads | VOL | | | 0.4 | V | VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; -55°C to 125°C | 5 |
| Input leakage current A, B, R | II | -1 | | 1 | µA | VI = VCC or GND; VCC = 6 V; -55°C to 125°C | 5 |
| Input leakage current RXCX | II | -0.5 | | 0.5 | µA | VCC = 6 V; -55°C to 125°C; Note 6 | 5 |
| Quiescent device current | ICC | | | 160 | µA | VI = VCC or GND; IO = 0; VCC = 6 V; -55°C to 125°C | 5 |
| Active device current | ICC | | | 1 | mA | Q = High & pins 2, 14 at VCC/4; VI = VCC or GND; IO = 0; VCC = 6 V; -55°C to 125°C | 5 |
| Input pulse width, A or B | tWH, tWL | 120 | | | ns | VCC = 2 V; -55°C to 125°C | 6 |
| Input pulse width, A or B | tWH, tWL | 24 | | | ns | VCC = 4.5 V; -55°C to 125°C | 6 |
| Input pulse width, A or B | tWH, tWL | 20 | | | ns | VCC = 6 V; -55°C to 125°C | 6 |
| Input pulse width, R | tWL | 120 | | | ns | VCC = 2 V; -55°C to 125°C | 6 |
| Input pulse width, R | tWL | 24 | | | ns | VCC = 4.5 V; -55°C to 125°C | 6 |
| Input pulse width, R | tWL | 20 | | | ns | VCC = 6 V; -55°C to 125°C | 6 |
| Reset recovery time | tREC | 5 | | | ns | VCC = 2 V; -55°C to 125°C | 6 |
| Propagation delay A, B to Q | tPLH | | | 375 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 |
| Propagation delay A, B to Q | tPLH | | | 75 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 |
| Propagation delay A, B to Q | tPLH | | | 64 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 |
| Propagation delay R to Q | tPHL | | | 375 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 |
| Propagation delay R to Q | tPHL | | | 75 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 |
| Propagation delay R to Q | tPHL | | | 64 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 |
| Output transition time | tTLH, tTHL | | | 110 | ns | CL = 50 pF; VCC = 2 V; -55°C to 125°C | 7 |
| Output transition time | tTLH, tTHL | | | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55°C to 125°C | 7 |
| Output transition time | tTLH, tTHL | | | 19 | ns | CL = 50 pF; VCC = 6 V; -55°C to 125°C | 7 |
| Output pulse width | τ | 0.595 | | 0.805 | ms | VCC = 5 V; RX = 10 kΩ, CX = 0.1 µF; CL = 50 pF; -55°C to 125°C | 7 |
| Output pulse width match | | -1 | | 1 | % | Same package | 7 |
## CAD (KiCad official)
- Symbol: `CD74HC4538NSR`
- Footprint: `Adom_Gen:Texas_Instruments_CD74`
- 3D model: SO-16-208mil (KiCad packages3D, STEP)
- 3D model files: `cd74hc4538nsr-etched.step` / `cd74hc4538nsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc4538nsr.step` / `cd74hc4538nsr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc4538nsr.pdf) (28 pp, sha256 `bf04c5a1ae827107`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hc4538nsr-datasheet.pdf)