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CD74HC4052NSR

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Texas Instruments Analog Switches / Multiplexers, SO-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74HC4052NSR

Texas Instruments · Analog Switches / Multiplexers · SO-16-300mil

CD74HC4052NSR from Texas Instruments, in a SO-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH B0 passive Channel B0 analog in/out of the B switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
2 CH B2 passive Channel B2 analog in/out of the B switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
3 COM B passive B common analog out/in that connects to one of the B channels selected by S0 and S1 when E is low.
4 CH B3 passive Channel B3 analog in/out of the B switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
5 CH B1 passive Channel B1 analog in/out of the B switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
6 E input Enable channels, active low; when high it disables all switches into the off state.
7 VEE power_in Negative power input, 0 V to -6 V per the recommended operating conditions.
8 GND power_in Ground reference for all digital control inputs and for the voltages referenced in the datasheet.
9 S1 input Channel select 1 digital input that selects the B and A channel per Table 2 of the datasheet.
10 S0 input Channel select 0 digital input that selects the B and A channel per Table 2 of the datasheet.
11 CH A3 passive Channel A3 analog in/out of the A switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
12 CH A0 passive Channel A0 analog in/out of the A switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
13 COM A passive A common analog in/out that connects to one of the A channels selected by S0 and S1 when E is low.
14 CH A1 passive Channel A1 analog in/out of the A switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
15 CH A2 passive Channel A2 analog in/out of the A switch bank, a bidirectional transmission gate that can pass analog signals from VEE to VCC.
16 VCC power_in Positive power input, 2 V to 6 V for HC types and 4.5 V to 5.5 V for HCT types per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SO-16-300mil
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage (VCC, VEE) VCC, VEE -0.5 10.5 V 6
DC supply voltage VCC -0.5 7 V 6
DC supply voltage VEE -7 V 6
DC input diode current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 6
DC switch diode current IOK -20 20 mA VI < VEE, 0.5 V or VI > VCC + 0.5 V 6
DC switch current -25 25 mA VI > VEE, 0.5 V or VI < VCC + 0.5 V 6
DC VCC or ground current ICC -50 50 mA 6
DC VEE current IEE -20 mA 6
Maximum junction temperature TJMAX 150 °C 6
Maximum lead temperature soldering 10 s TLMAX 300 °C Soldering 10 s 6
Junction temperature TJ 150 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage range (HC types) VCC 2 6 V CD54 and 74HC types; TA = full package temperature range 6
Supply voltage range VCC, VEE (HC types) VCC, VEE 2 10 V CD54 and 74HC types, see Figure 1 6
Supply voltage range VEE (HC types) VEE 0 -6 V CD54 and 74HC types, see Figure 2 6
Operating temperature TA -55 125 °C Operating free-air temperature range 6
Input rise and fall times tr, tf 0 1000 ns VCC = 2 V 6
Input rise and fall times tr, tf 0 500 ns VCC = 4.5 V 6
Input rise and fall times tr, tf 0 400 ns VCC = 6 V 6
High-level input voltage VIH 1.5 V VCC = 2 V; TA = 25°C 7
High-level input voltage VIH 3.15 V VCC = 4.5 V; TA = 25°C 7
High-level input voltage VIH 4.2 V VCC = 6 V; TA = 25°C 7
Low-level input voltage VIL 0.5 V VCC = 2 V; TA = 25°C 7
Low-level input voltage VIL 1.35 V VCC = 4.5 V; TA = 25°C 7
Low-level input voltage VIL 1.8 V VCC = 6 V; TA = 25°C 7
ON resistance rON 70 160 Ω IO = 1 mA; VEE = 0 V; VCC = 4.5 V; TA = 25°C 8
ON resistance rON 200 Ω IO = 1 mA; VEE = 0 V; VCC = 4.5 V; TA = -40°C to +85°C 8
ON resistance rON 240 Ω IO = 1 mA; VEE = 0 V; VCC = 4.5 V; TA = -55°C to +125°C 8
ON resistance rON 60 140 Ω IO = 1 mA; VEE = 0 V; VCC = 6 V; TA = 25°C 8
ON resistance rON 175 Ω IO = 1 mA; VEE = 0 V; VCC = 6 V; TA = -40°C to +85°C 8
ON resistance rON 210 Ω IO = 1 mA; VEE = 0 V; VCC = 6 V; TA = -55°C to +125°C 8
ON resistance rON 40 120 Ω IO = 1 mA; VEE = -4.5 V; VCC = 4.5 V; TA = 25°C 8
ON resistance rON 150 Ω IO = 1 mA; VEE = -4.5 V; VCC = 4.5 V; TA = -40°C to +85°C 8
ON resistance rON 180 Ω IO = 1 mA; VEE = -4.5 V; VCC = 4.5 V; TA = -55°C to +125°C 8
Maximum ON resistance between any two channels ΔrON 10 Ω VEE = 0 V; VCC = 4.5 V; TA = 25°C 8
Maximum ON resistance between any two channels ΔrON 8.5 Ω VEE = 0 V; VCC = 6 V; TA = 25°C 8
Maximum ON resistance between any two channels ΔrON 5 Ω VEE = -4.5 V; VCC = 4.5 V; TA = 25°C 8
Control input leakage current IIL -0.1 0.1 µA VCC or GND; VCC = 6 V; TA = 25°C 9
Control input leakage current IIL -1 1 µA VCC or GND; VCC = 6 V; TA = -40°C to +85°C 9
Quiescent device current ICC 8 µA IO = 0; VIS = VEE, VOS = VCC; VCC or GND; VCC = 6 V; TA = 25°C 9
Quiescent device current ICC 80 µA IO = 0; VIS = VEE, VOS = VCC; VCC or GND; VCC = 6 V; TA = -40°C to +85°C 9
Quiescent device current ICC 160 µA IO = 0; VIS = VEE, VOS = VCC; VCC or GND; VCC = 6 V; TA = -55°C to +125°C 9
Junction-to-ambient thermal resistance RθJA 83 °C/W NS (SO) 16-pin package 7
Junction-to-case (top) thermal resistance RθJC(top) 41.2 °C/W NS (SO) 16-pin package 7
Junction-to-board thermal resistance RθJB 43.3 °C/W NS (SO) 16-pin package 7
Junction-to-top characterization parameter ψJT 9.2 °C/W NS (SO) 16-pin package 7
Junction-to-board characterization parameter ψJB 43 °C/W NS (SO) 16-pin package 7

CAD (KiCad official)

  • Symbol: CD74HC4052NSR
  • Footprint: Adom_Gen:Texas_Instruments_CD74
  • 3D model: SO-16-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74hc4052nsr-etched.step / cd74hc4052nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4052nsr.step / cd74hc4052nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (49 pp, sha256 f46801e69998f7f9, retrieved 2026-10-27, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF