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docs cd74hc4050m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hc4050m96: viewers · Ray
cd74hc4050m96-etched.fit.json cd74hc4050m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc4050m96-etched.glb cd74hc4050m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
cd74hc4050m96-etched.step cd74hc4050m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
cd74hc4050m96.glb Publish 0.1.0 · Ray
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cd74hc4050m96.step Publish 0.1.0 · Ray
package.json cd74hc4050m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
page.json cd74hc4050m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… · Ray
README.md Initial commit: component/cd74hc4050m96 · Ray

CD74HC4050M96

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-16

CD74HC4050M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply voltage pin, accepts 2V to 6V for HC types
2 1Y output Non-inverting buffer output for stage 1, output range 0V to VCC
3 1A input Input for buffer stage 1, accepts logic levels 0V to 15V for level translation capability
4 2Y output Non-inverting buffer output for stage 2, output range 0V to VCC
5 2A input Input for buffer stage 2, accepts logic levels 0V to 15V for level translation capability
6 3Y output Non-inverting buffer output for stage 3, output range 0V to VCC
7 GND power_in Ground reference voltage
8 3A input Input for buffer stage 3, accepts logic levels 0V to 15V for level translation capability
9 NC unconnected No connection
10 6A input Input for buffer stage 6, accepts logic levels 0V to 15V for level translation capability
11 NC unconnected No connection
12 5Y output Non-inverting buffer output for stage 5, output range 0V to VCC
13 5A input Input for buffer stage 5, accepts logic levels 0V to 15V for level translation capability
14 4Y output Non-inverting buffer output for stage 4, output range 0V to VCC
15 4A input Input for buffer stage 4, accepts logic levels 0V to 15V for level translation capability
16 6Y output Non-inverting buffer output for stage 6, output range 0V to VCC

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC4050M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc4050m96-etched.step / cd74hc4050m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4050m96.step / cd74hc4050m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 2d5643ffe4911f23, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF