CD74HC4049E from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Supply voltage, 2V to 6V for HC types (absolute max 7V).
2	1Y	output	Buffer 1 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
3	1A	input	Buffer 1 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
4	2Y	output	Buffer 2 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
5	2A	input	Buffer 2 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
6	3Y	output	Buffer 3 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
7	3A	input	Buffer 3 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
8	GND	power_in	Ground (0V) reference.
9	4A	input	Buffer 4 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
10	4Y	output	Buffer 4 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
11	5A	input	Buffer 5 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
12	5Y	output	Buffer 5 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
13	NC	unconnected	No internal connection.
14	6A	input	Buffer 6 input, accepts logic levels up to 15V (absolute max 16V) for high-to-low level conversion.
15	6Y	output	Buffer 6 inverting output, swings 0V to VCC and drives 10 LSTTL loads.
16	NC	unconnected	No internal connection.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	PDIP-16
Category	Logic ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Supply Voltage	VCC	-0.5		7	V		3
Input Voltage Range	VI	-0.5		16	V		3
DC Input Diode Current	IIK			-20	mA	For VI < -0.5V	3
DC Output Diode Current	IOK	-20		20	mA	For VO < -0.5V or VO > VCC + 0.5V	3
DC Output Source or Sink Current per Output Pin	IO	-25		25	mA	For VO > -0.5V or VO < VCC + 0.5V	3
DC VCC or Ground Current	ICC, IGND	-50		50	mA		3
Maximum Junction Temperature (Plastic Package)	TJ			150	°C	Plastic package	3
Storage Temperature Range	Tstg	-65		150	°C		3
Maximum Lead Temperature				300	°C	Soldering 10s	3
Operating Temperature Range	TA	-55		125	°C		3
Supply Voltage Range	VCC	2		6	V	HC Types	3
DC Input Voltage	VI	0		15	V		3
DC Output Voltage	VO	0			V	0V to VCC	3
Input Rise and Fall Time	tr, tf			1000	ns	VCC = 2V	3
Input Rise and Fall Time	tr, tf			500	ns	VCC = 4.5V	3
Input Rise and Fall Time	tr, tf			400	ns	VCC = 6V	3
High Level Input Voltage	VIH	1.5			V	VCC = 2V, -55 to 125°C	3
High Level Input Voltage	VIH	3.15			V	VCC = 4.5V, -55 to 125°C	3
High Level Input Voltage	VIH	4.2			V	VCC = 6V, -55 to 125°C	3
Low Level Input Voltage	VIL			0.5	V	VCC = 2V, -55 to 125°C	3
Low Level Input Voltage	VIL			1.35	V	VCC = 4.5V, -55 to 125°C	3
Low Level Input Voltage	VIL			1.8	V	VCC = 6V, -55 to 125°C	3
High Level Output Voltage, CMOS Loads	VOH	1.9			V	VI = VIH or VIL, IO = -0.02mA, VCC = 2V, -55 to 125°C	3
High Level Output Voltage, CMOS Loads	VOH	4.4			V	VI = VIH or VIL, IO = -0.02mA, VCC = 4.5V, -55 to 125°C	3
High Level Output Voltage, CMOS Loads	VOH	5.9			V	VI = VIH or VIL, IO = -0.02mA, VCC = 6V, -55 to 125°C	3
High Level Output Voltage, TTL Loads	VOH	3.7			V	IO = -4mA, VCC = 4.5V, -55 to 125°C	3
High Level Output Voltage, TTL Loads	VOH	5.2			V	IO = -5.2mA, VCC = 6V, -55 to 125°C	3
Low Level Output Voltage, CMOS Loads	VOL			0.1	V	VI = VIH or VIL, IO = 0.02mA, VCC = 2V, -55 to 125°C	3
Low Level Output Voltage, TTL Loads	VOL			0.4	V	IO = 4mA, VCC = 4.5V, -55 to 125°C	3
Input Leakage Current	II	-1		1	µA	VI = VCC or GND, VCC = 6V, -55 to 125°C	3
Input Leakage Current	II	-5		5	µA	VI = 15V, VCC = 6V, -55 to 125°C	3
Quiescent Device Current	ICC			40	µA	VI = VCC or GND, IO = 0, VCC = 6V, -55 to 125°C	4
Propagation Delay, nA to nY	tPLH, tPHL			130	ns	CL = 50pF, VCC = 2V, -55 to 125°C	4
Propagation Delay, nA to nY	tPLH, tPHL			26	ns	CL = 50pF, VCC = 4.5V, -55 to 125°C	4
Propagation Delay, nA to nY	tPLH, tPHL			22	ns	CL = 50pF, VCC = 6V, -55 to 125°C	4
Propagation Delay, nA to nY	tPLH, tPHL		6		ns	CL = 15pF, VCC = 5V, 25°C	4
Transition Times	tTLH, tTHL			110	ns	CL = 50pF, VCC = 2V, -55 to 125°C	4
Transition Times	tTLH, tTHL			22	ns	CL = 50pF, VCC = 4.5V, -55 to 125°C	4
Transition Times	tTLH, tTHL			19	ns	CL = 50pF, VCC = 6V, -55 to 125°C	4
Input Capacitance	CI			10	pF	-55 to 125°C	4
Power Dissipation Capacitance	CPD		35		pF	VCC = 5V, 25°C, per gate	4

CAD (KiCad official)

Symbol: CD74HC4049E
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: PDIP-16 (KiCad packages3D, STEP)
3D model files: cd74hc4049e-etched.step / cd74hc4049e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4049e.step / cd74hc4049e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (11 pp, sha256 0cce27c0d5d4f193, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CD74HC4049E

Verified CD74HC4049E

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README