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CD74HC4046APWR
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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC4046APWR++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16++CD74HC4046APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PCPOUT | output | Phase comparator pulse output; the datasheet names this function but gives no electrical limits for this pin. |+| 2 | PC1OUT | output | Phase comparator 1 output, which is an Exclusive-OR network whose average output is filtered to the VCO input. |+| 3 | COMPIN | input | Comparator input that receives the VCO output, either directly or through a frequency divider, for comparison with SIGIN. |+| 4 | VCOOUT | output | VCO output with a specified 50% duty factor, connectable directly to COMPIN or through a frequency divider. |+| 5 | INH | input | Inhibit input where a LOW level enables the VCO and demodulator and a HIGH level turns both off to minimize standby power consumption. |+| 6 | C1A | passive | Connection A for external capacitor C1, which together with R1 determines the VCO frequency range. |+| 7 | C1B | passive | Connection B for external capacitor C1, connected between C1A and C1B. |+| 8 | GND | power_in | Ground (0V) reference for the device. |+| 9 | VCOIN | input | VCO input with high input impedance, which simplifies low-pass filter design. |+| 10 | DEMOUT | output | Demodulator output equal to the VCO input voltage; if used a load resistor RS should go from DEMOUT to GND, and if unused it should be left open. |+| 11 | R1 | passive | Resistor R1 connection, where R1 to GND together with C1 sets the VCO frequency range. |+| 12 | R2 | passive | Resistor R2 connection, where R2 to GND gives the VCO a frequency offset if required. |+| 13 | PC2OUT | output | Phase comparator 2 output; with no signal at SIGIN the VCO adjusts to fMIN. |+| 14 | SIGIN | input | Signal input that can be directly coupled within the HC family input logic levels, or capacitively coupled for smaller signal swings. |+| 15 | PC3OUT | output | Phase comparator 3 output; with no signal at SIGIN the VCO adjusts to fMAX. |+| 16 | VCC | power_in | Positive supply voltage; the VCO section is specified for 3V to 6V and the digital section for 2V to 6V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC4046APWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc4046apwr-etched.step` / `cd74hc4046apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc4046apwr.step` / `cd74hc4046apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc4046a.pdf) (36 pp, sha256 `047ac408a2e3bcfc`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc4046apwr-datasheet.pdf)
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the datasheet names this function but gives no electrical limits for this pin."+ },+ {+ "number": "2",+ "name": "PC1OUT",+ "type": "output",+ "description": "Phase comparator 1 output, which is an Exclusive-OR network whose average output is filtered to the VCO input."+ },+ {+ "number": "3",+ "name": "COMPIN",+ "type": "input",+ "description": "Comparator input that receives the VCO output, either directly or through a frequency divider, for comparison with SIGIN."+ },+ {+ "number": "4",+ "name": "VCOOUT",+ "type": "output",+ "description": "VCO output with a specified 50% duty factor, connectable directly to COMPIN or through a frequency divider."+ },+ {+ "number": "5",+ "name": "INH",+ "type": "input",+ "description": "Inhibit input where a LOW level enables the VCO and demodulator and a HIGH level turns both off to minimize standby power consumption."+ },+ {+ "number": "6",+ "name": "C1A",+ "type": "passive",+ "description": "Connection A for external capacitor C1, which together with R1 determines the VCO frequency range."+ },+ {+ "number": "7",+ "name": "C1B",+ "type": "passive",+ "description": "Connection B for external capacitor C1, connected between C1A and C1B."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0V) reference for the device."+ },+ {+ "number": "9",+ "name": "VCOIN",+ "type": "input",+ "description": "VCO input with high input impedance, which simplifies low-pass filter design."+ },+ {+ "number": "10",+ "name": "DEMOUT",+ "type": "output",+ "description": "Demodulator output equal to the VCO input voltage; if used a load resistor RS should go from DEMOUT to GND, and if unused it should be left open."+ },+ {+ "number": "11",+ "name": "R1",+ "type": "passive",+ "description": "Resistor R1 connection, where R1 to GND together with C1 sets the VCO frequency range."+ },+ {+ "number": "12",+ "name": "R2",+ "type": "passive",+ "description": "Resistor R2 connection, where R2 to GND gives the VCO a frequency offset if required."+ },+ {+ "number": "13",+ "name": "PC2OUT",+ "type": "output",+ "description": "Phase comparator 2 output; with no signal at SIGIN the VCO adjusts to fMIN."+ },+ {+ "number": "14",+ "name": "SIGIN",+ "type": "input",+ "description": "Signal input that can be directly coupled within the HC family input logic levels, or capacitively coupled for smaller signal swings."+ },+ {+ "number": "15",+ "name": "PC3OUT",+ "type": "output",+ "description": "Phase comparator 3 output; with no signal at SIGIN the VCO adjusts to fMAX."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; the VCO section is specified for 3V to 6V and the digital section for 2V to 6V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout is shared by the PDIP, SOIC, SOP and TSSOP variants of the CD74HC4046A on page 2; the TSS; The datasheet's pin table gives names and functions only for PCPOUT, so its description is limited t"+ ],+ "pages_sent": 7,+ "cost_usd": 0.0598,+ "at": "2026-10-07T21:34:30"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd74hc4046a.pdf",+ "pages": 36,+ "sha256": "047ac408a2e3bcfc",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hc4046apwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hc4046apwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5e1005eeeff2573b84e8c036f2c9d5d1fbe4926fbe9cec2e94a827f74d85d1ad",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}