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CD74HC4040M96

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Texas Instruments Counters / Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC4040M96

Texas Instruments · Counters / Dividers · SOIC-16

CD74HC4040M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output Buffered counter output of stage 12, which can drive 10 LSTTL loads (standard output).
2 Q6 output Buffered counter output of stage 6, which can drive 10 LSTTL loads (standard output).
3 Q5 output Buffered counter output of stage 5, which can drive 10 LSTTL loads (standard output).
4 Q7 output Buffered counter output of stage 7, which can drive 10 LSTTL loads (standard output).
5 Q4 output Buffered counter output of stage 4, which can drive 10 LSTTL loads (standard output).
6 Q3 output Buffered counter output of stage 3, which can drive 10 LSTTL loads (standard output).
7 Q2 output Buffered counter output of stage 2, which can drive 10 LSTTL loads (standard output).
8 GND power_in Ground reference for the device; continuous current through VCC or GND is limited to ±50 mA.
9 Q1' output Buffered output of the first counter stage, which can drive 10 LSTTL loads (standard output).
10 CP input Clock (input pulses) input, buffered; the counter advances one count on each negative clock transition.
11 MR input Master reset input, buffered; a high level resets all counters to the zero state (all outputs low).
12 Q9 output Buffered counter output of stage 9, which can drive 10 LSTTL loads (standard output).
13 Q8 output Buffered counter output of stage 8, which can drive 10 LSTTL loads (standard output).
14 Q10 output Buffered counter output of stage 10, which can drive 10 LSTTL loads (standard output).
15 Q11 output Buffered counter output of stage 11, which can drive 10 LSTTL loads (standard output).
16 VCC power_in Positive supply, 2 V to 6 V for HC types, with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (HC types) VCC 2 6 V HC types 4
DC input or output voltage VI, VO 0 V max VCC 4
Input rise and fall time tr, tf 1000 ns VCC = 2 V 4
Input rise and fall time tr, tf 500 ns VCC = 4.5 V 4
Input rise and fall time tr, tf 400 ns VCC = 6 V 4
Temperature range TA -55 125 ℃ 4
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output source or sink current per output pin IO -25 25 mA VO > -0.5 V or VCC + 0.5 V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 73 °C/W D (SOIC) 16 pins 4
High level input voltage VIH 1.5 V VCC = 2 V 5
High level input voltage VIH 3.15 V VCC = 4.5 V 5
High level input voltage VIH 4.2 V VCC = 6 V 5
Low level input voltage VIL 0.5 V VCC = 2 V 5
Low level input voltage VIL 1.35 V VCC = 4.5 V 5
Low level input voltage VIL 1.8 V VCC = 6 V 5
High level output voltage, CMOS loads VOH 1.9 V IOH = -20 µA, VCC = 2 V 5
High level output voltage, CMOS loads VOH 4.4 V IOH = -20 µA, VCC = 4.5 V 5
High level output voltage, CMOS loads VOH 5.9 V IOH = -20 µA, VCC = 6 V 5
High level output voltage, TTL loads VOH 3.7 V IOH = -4 mA, VCC = 4.5 V 5
High level output voltage, TTL loads VOH 5.2 V IOH = -5.2 mA, VCC = 6 V 5
Low level output voltage, CMOS loads VOL 0.1 V IOL = 20 µA, VCC = 2 V 5
Low level output voltage, TTL loads VOL 0.4 V IOL = 4 mA, VCC = 4.5 V 5
Input leakage current II -1 1 µA VCC or GND, VCC = 6 V 5
Supply current ICC 8 160 µA VCC or GND, VCC = 6 V 5
Maximum input pulse frequency fMAX 4 MHz VCC = 2 V 6
Maximum input pulse frequency fMAX 20 MHz VCC = 4.5 V 6
Maximum input pulse frequency fMAX 24 MHz VCC = 6 V 6
Input pulse width tW 120 ns VCC = 2 V 6
Input pulse width tW 24 ns VCC = 4.5 V 6
Input pulse width tW 20 ns VCC = 6 V 6
Reset removal time tREM 75 ns VCC = 2 V 6
Reset removal time tREM 15 ns VCC = 4.5 V 6
Reset removal time tREM 13 ns VCC = 6 V 6
Reset pulse width tW 120 ns VCC = 2 V 6
Reset pulse width tW 24 ns VCC = 4.5 V 6
Reset pulse width tW 20 ns VCC = 6 V 6
Propagation delay time CP to Q1' output tPLH, tPHL 140 210 ns CL = 50 pF, VCC = 2 V 6
Propagation delay time CP to Q1' output tPLH, tPHL 28 42 ns CL = 50 pF, VCC = 4.5 V 6
Propagation delay time CP to Q1' output tPLH, tPHL 24 36 ns CL = 50 pF, VCC = 6 V 6
Propagation delay time Qn to Qn+1 tPLH, tPHL 75 110 ns CL = 50 pF, VCC = 2 V 6
Propagation delay time Qn to Qn+1 tPLH, tPHL 15 22 ns CL = 50 pF, VCC = 4.5 V 6
Propagation delay time Qn to Qn+1 tPLH, tPHL 13 19 ns CL = 50 pF, VCC = 6 V 6
Propagation delay time MR to Qn tPLH, tPHL 170 255 ns CL = 50 pF, VCC = 2 V 6
Propagation delay time MR to Qn tPLH, tPHL 34 51 ns CL = 50 pF, VCC = 4.5 V 6
Propagation delay time MR to Qn tPLH, tPHL 29 43 ns CL = 50 pF, VCC = 6 V 6
Output transition time tTLH, tTHL 75 110 ns CL = 50 pF, VCC = 2 V 6
Output transition time tTLH, tTHL 15 22 ns CL = 50 pF, VCC = 4.5 V 6
Output transition time tTLH, tTHL 13 19 ns CL = 50 pF, VCC = 6 V 6
Input capacitance CIN 10 pF CL = 50 pF 6
Power dissipation capacitance CPD 40 pF CL = 15 pF, VCC = 5 V 6

CAD (KiCad official)

  • Symbol: CD74HC4040M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc4040m96-etched.step / cd74hc4040m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4040m96.step / cd74hc4040m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 85aaba4669d66cf5, retrieved 2026-10-27, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF