# CD74HC4024M96

**Texas Instruments** · Counters, Dividers · SOIC-14

CD74HC4024M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP | input | Clock input; the counter advances one count on each negative (high-to-low) transition, with buffered input. |
| 2 | MR | input | Master reset input; a high level resets all counter stages to zero and forces all outputs low. |
| 3 | Q7 | output | Buffered counter stage 7 output. |
| 4 | Q6 | output | Buffered counter stage 6 output. |
| 5 | Q5 | output | Buffered counter stage 5 output. |
| 6 | Q4 | output | Buffered counter stage 4 output. |
| 7 | GND | power_in | Ground reference. |
| 8 | NC | unconnected | No internal connection. |
| 9 | Q3 | output | Buffered counter stage 3 output. |
| 10 | NC | unconnected | No internal connection. |
| 11 | Q2 | output | Buffered counter stage 2 output. |
| 12 | Q1' | output | Buffered counter stage 1 output (CP to Q1' propagation delay specified). |
| 13 | NC | unconnected | No internal connection. |
| 14 | VCC | power_in | Supply voltage: 2 V to 6 V for HC types, absolute maximum 7 V; bypass with 0.1 µF capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V; -55 to 125 ℃ | 5 |
| High level input voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V; -55 to 125 ℃ | 5 |
| High level input voltage | VIH | 4.2 |  |  | V | VCC = 6 V; -55 to 125 ℃ | 5 |
| Low level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V; -55 to 125 ℃ | 5 |
| Low level input voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V; -55 to 125 ℃ | 5 |
| Low level input voltage | VIL |  |  | 1.8 | V | VCC = 6 V; -55 to 125 ℃ | 5 |
| High level output voltage, CMOS loads | VOH | 1.9 |  |  | V | IOH = -20 μA; VCC = 2 V; -55 to 125 ℃ | 5 |
| High level output voltage, CMOS loads | VOH | 4.4 |  |  | V | IOH = -20 μA; VCC = 4.5 V; -55 to 125 ℃ | 5 |
| High level output voltage, CMOS loads | VOH | 5.9 |  |  | V | IOH = -20 μA; VCC = 6 V; -55 to 125 ℃ | 5 |
| High level output voltage, TTL loads | VOH | 3.7 |  |  | V | IOH = -4 mA; VCC = 4.5 V; -55 to 125 ℃ | 5 |
| High level output voltage, TTL loads | VOH | 5.2 |  |  | V | IOH = -5.2 mA; VCC = 6 V; -55 to 125 ℃ | 5 |
| Low level output voltage, CMOS loads | VOL |  |  | 0.1 | V | IOL = 20 μA; VCC = 2 V; -55 to 125 ℃ | 5 |
| Low level output voltage, TTL loads | VOL |  |  | 0.4 | V | IOL = 4 mA; VCC = 4.5 V; -55 to 125 ℃ | 5 |
| Input leakage current | II | -1 | 0.1 | 1 | μA | VCC or GND; VCC = 6 V; -55 to 125 ℃ | 5 |
| Quiescent device current | ICC |  | 8 | 160 | μA | VCC or GND; VCC = 6 V; -55 to 125 ℃ | 5 |
| Propagation delay time, CP to Q1' output | tPLH, tPHL |  |  | 210 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 |
| Propagation delay time, CP to Q1' output | tPLH, tPHL |  |  | 42 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 |
| Propagation delay time, CP to Q1' output | tPLH, tPHL |  |  | 36 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 |
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL |  |  | 110 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 |
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL |  |  | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 |
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL |  |  | 19 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 |
| Propagation delay time, MR to Qn | tPLH, tPHL |  |  | 255 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 |
| Propagation delay time, MR to Qn | tPLH, tPHL |  |  | 51 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 |
| Propagation delay time, MR to Qn | tPLH, tPHL |  |  | 43 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 |
| Output transition time | tTLH, tTHL |  |  | 110 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 |
| Output transition time | tTLH, tTHL |  |  | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 |
| Output transition time | tTLH, tTHL |  |  | 19 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 |
| Input capacitance | CIN |  |  | 10 | pF | CL = 50 pF; -55 to 125 ℃ | 7 |
| Maximum input pulse frequency | fMAX | 4 |  |  | MHz | VCC = 2 V; -55 to 125 ℃ | 6 |
| Maximum input pulse frequency | fMAX | 20 |  |  | MHz | VCC = 4.5 V; -55 to 125 ℃ | 6 |
| Maximum input pulse frequency | fMAX | 24 |  |  | MHz | VCC = 6 V; -55 to 125 ℃ | 6 |
| Input pulse width | tW | 120 |  |  | ns | VCC = 2 V; -55 to 125 ℃ | 6 |
| Input pulse width | tW | 24 |  |  | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 |
| Input pulse width | tW | 20 |  |  | ns | VCC = 6 V; -55 to 125 ℃ | 6 |
| Reset removal time | tREM | 75 |  |  | ns | VCC = 2 V; -55 to 125 ℃ | 6 |
| Reset removal time | tREM | 15 |  |  | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 |
| Resetools removal time | tREM | 13 |  |  | ns | VCC = 6 V; -55 to 125 ℃ | 6 |
| Reset pulse width | tW | 120 |  |  | ns | VCC = 2 V; -55 to 125 ℃ | 6 |
| Reset pulse width | tW | 24 |  |  | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 |
| Reset pulse width | tW | 20 |  |  | ns | VCC = 6 V; -55 to 125 ℃ | 6 |
| Supply voltage range, HC types | VCC | 2 |  | 6 | V | HC types | 4 |
| DC input or output voltage | VI, VO | 0 |  |  | V | Maximum printed as VCC | 4 |
| Input rise and fall time | tt |  |  | 1000 | ns | VCC = 2 V | 4 |
| Input rise and fall time | tt |  |  | 500 | ns | VCC = 4.5 V | 4 |
| Input rise and fall time | tt |  |  | 400 | ns | VCC = 6 V | 4 |
| Temperature range | TA | -55 |  | 125 | ℃ |  | 4 |
| Supply voltage | VCC | -0.5 |  | 7 | V |  | 4 |
| Input diode current | IIK | -20 |  | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output diode current | IOK | -20 |  | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Output source or sink current per output pin | IO | -25 |  | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 4 |
| Junction temperature | TJ |  |  | 150 | ℃ |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | ℃ |  | 4 |
| Lead temperature (soldering) |  |  |  | 300 | ℃ | 10 s; SOIC lead tips only | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 86 |  | °C/W | D (SOIC) package, 14 pins | 4 |

## CAD (KiCad official)

- Symbol: `CD74HC4024M96`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `cd74hc4024m96-etched.step` / `cd74hc4024m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc4024m96.step` / `cd74hc4024m96.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74hc4024m96.pdf) (25 pp, sha256 `abd021ad2b57cd1b`, retrieved 2026-10-17, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd74hc4024m96-datasheet.pdf)